Trying to verify Verilog/VHDL designs with formal methods and tools
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[options]
mode prove
depth 20
# falis with multiclock disabled
multiclock off
[engines]
smtbmc
[script]
verific -vhdl dlatch.vhd
verific -formal dlatch_t.sv
prep -top dlatch_t
[files]
dlatch.vhd
dlatch_t.sv