From 012de1f86802150c9ea2f8eb00d10b4854b3315c Mon Sep 17 00:00:00 2001 From: tmeissner Date: Tue, 27 Dec 2022 01:08:46 +0100 Subject: [PATCH] RTL refactoring --- blink/rtl/blink.vhd | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/blink/rtl/blink.vhd b/blink/rtl/blink.vhd index 0867b73..94a63f5 100644 --- a/blink/rtl/blink.vhd +++ b/blink/rtl/blink.vhd @@ -29,8 +29,6 @@ architecture rtl of blink is signal s_rst_n : std_logic; signal s_cfg_end : std_logic; - signal s_led : unsigned(led_n_o'range); - begin pll : CC_PLL @@ -74,14 +72,12 @@ begin process (s_pll_clk, s_rst_n) is begin if (not s_rst_n) then - s_led <= x"01"; + led_n_o <= x"FE"; elsif (rising_edge(s_pll_clk)) then if (s_clk_en) then - s_led <= s_led(6 downto 0) & s_led(7); + led_n_o <= led_n_o(6 downto 0) & led_n_o(7); end if; end if; end process; - led_n_o <= not std_logic_vector(s_led); - end architecture;