From 32fa71a90b5ed32d2064a3eafb58f5beb0ab8c18 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Fri, 30 Dec 2022 18:47:20 +0100 Subject: [PATCH] Increase pll clock to 10 MHz, add uart_loop design to readme --- README.md | 6 ++++++ uart_loop/rtl/uart_loop.vhd | 15 ++++++--------- uart_loop/sim/Makefile | 2 +- uart_loop/syn/Makefile | 2 +- uart_loop/syn/tb_uart_loop.v | 4 ++-- uart_reg/rtl/uart_reg.vhd | 6 +++--- uart_reg/syn/tb_uart_reg.v | 2 +- 7 files changed, 20 insertions(+), 17 deletions(-) diff --git a/README.md b/README.md index 923e947..4588d4d 100644 --- a/README.md +++ b/README.md @@ -8,6 +8,12 @@ Ongoing experiments with the Cologne Chip's GateMate FPGA architecture. All expe Simple design which should display a blinking LED waving from LED1-LED8 of the GateMate FPGA Starter Kit. It uses *CC_PLL* & *CC_CFG_END* primitives of the GateMate FPGA. +### uart_loop + +Simple UART loop with UART RX & TX units and FIFO buffer between. It uses *CC_PLL* & *CC_CFG_END* primitives of the GateMate FPGA. With fifo depth >= 18 Yosys is infering *CC_BRAM_20K* instead of registers. + +Beware: The simulation model of *CC_BRAM_20K* seems to be incorrect, so better set fifo depth < 18 or use yosys option `-nobram` when synthesizing the model for post-synthesis & post-implementation simulation. + ### uart_reg Register file which can be accessed through UART. It uses *CC_PLL* & *CC_CFG_END* primitives of the GateMate FPGA. It contains 8 registers storing values of one byte each. The first received byte on the axis in port contains command & address: diff --git a/uart_loop/rtl/uart_loop.vhd b/uart_loop/rtl/uart_loop.vhd index e03c3c8..ce149db 100644 --- a/uart_loop/rtl/uart_loop.vhd +++ b/uart_loop/rtl/uart_loop.vhd @@ -1,8 +1,5 @@ --- This design implements a register file which can --- be accessed by an UART with 9600 baud --- --- See into uart_ctrl.vhd for documentation of the protocol --- used to read / write the register file. +-- Simple UART loop with UART RX & TX units and FIFO buffer +-- between. It's working at baudrate 9600. library ieee ; @@ -44,7 +41,7 @@ begin pll : CC_PLL generic map ( REF_CLK => "10", - OUT_CLK => "1", + OUT_CLK => "10", PERF_MD => "ECONOMY" ) port map ( @@ -68,7 +65,7 @@ begin uart_rx : entity work.uart_rx generic map ( - CLK_DIV => 104 + CLK_DIV => 1040 ) port map ( -- globals @@ -84,7 +81,7 @@ begin axis_fifo : entity work.axis_fifo generic map ( - DEPTH => 64, + DEPTH => 16, WIDTH => 8 ) port map ( @@ -107,7 +104,7 @@ begin uart_tx : entity work.uart_tx generic map ( - CLK_DIV => 104 + CLK_DIV => 1040 ) port map ( -- globals diff --git a/uart_loop/sim/Makefile b/uart_loop/sim/Makefile index b280847..1e439fb 100644 --- a/uart_loop/sim/Makefile +++ b/uart_loop/sim/Makefile @@ -20,7 +20,7 @@ tb_${DESIGN_NAME}: ${LIB_SRC} ${RTL_SRC} ${SIM_SRC} sim: tb_${DESIGN_NAME} @echo "Run testbench ..." - ghdl -r ${SIM_FLAGS} -Pwork tb_${DESIGN_NAME} --assert-level=error + ghdl -r ${SIM_FLAGS} -Pwork tb_${DESIGN_NAME} --assert-level=error --wave=tb_${DESIGN_NAME}.ghw work: mkdir $@ diff --git a/uart_loop/syn/Makefile b/uart_loop/syn/Makefile index 6bfb630..3e44100 100644 --- a/uart_loop/syn/Makefile +++ b/uart_loop/syn/Makefile @@ -2,7 +2,7 @@ DESIGN_NAME := uart_loop WORK_FILES := ../../lib/user_components.vhd ../rtl/uart_tx.vhd ../rtl/uart_rx.vhd ../rtl/${DESIGN_NAME}.vhd GM_FILES := ../../lib/rtl_components.vhd GHDL_FLAGS := --std=08 --workdir=build -Pbuild -YOSYSPIPE := -nomx8 -retime -nobram +YOSYSPIPE := -nomx8 -retime # ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate? PNRFLAGS := -om 2 PNRTOOL := $(shell which p_r) diff --git a/uart_loop/syn/tb_uart_loop.v b/uart_loop/syn/tb_uart_loop.v index 1016252..1d96441 100644 --- a/uart_loop/syn/tb_uart_loop.v +++ b/uart_loop/syn/tb_uart_loop.v @@ -18,8 +18,8 @@ module CC_PLL #( reg r_pll_clk; reg r_user_pll_locked; - // OUT_FREQ = 1 MHz - integer clk_half_period = 500; + // OUT_FREQ = 10 MHz + integer clk_half_period = 50; initial begin r_pll_clk = 1'b0; diff --git a/uart_reg/rtl/uart_reg.vhd b/uart_reg/rtl/uart_reg.vhd index 89bc0b2..8d30e84 100644 --- a/uart_reg/rtl/uart_reg.vhd +++ b/uart_reg/rtl/uart_reg.vhd @@ -44,7 +44,7 @@ begin pll : CC_PLL generic map ( REF_CLK => "10", - OUT_CLK => "1", + OUT_CLK => "10", PERF_MD => "ECONOMY" ) port map ( @@ -68,7 +68,7 @@ begin uart_rx : entity work.uart_rx generic map ( - CLK_DIV => 104 + CLK_DIV => 1040 ) port map ( -- globals @@ -99,7 +99,7 @@ begin uart_tx : entity work.uart_tx generic map ( - CLK_DIV => 104 + CLK_DIV => 1040 ) port map ( -- globals diff --git a/uart_reg/syn/tb_uart_reg.v b/uart_reg/syn/tb_uart_reg.v index 9756226..00b727e 100644 --- a/uart_reg/syn/tb_uart_reg.v +++ b/uart_reg/syn/tb_uart_reg.v @@ -19,7 +19,7 @@ module CC_PLL #( reg r_user_pll_locked; // OUT_FREQ = 1 MHz - integer clk_half_period = 500; + integer clk_half_period = 50; initial begin r_pll_clk = 1'b0;