From 3b6a315a0d399e6ab213eac43755d5fa6413f1aa Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Wed, 28 Dec 2022 12:23:15 +0100
Subject: [PATCH] Add user_components.vhd containing generic RTL modules

---
 blink/syn/Makefile      |  5 +++--
 lib/user_components.vhd | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 43 insertions(+), 2 deletions(-)
 create mode 100644 lib/user_components.vhd

diff --git a/blink/syn/Makefile b/blink/syn/Makefile
index 80c5b68..c0c866e 100644
--- a/blink/syn/Makefile
+++ b/blink/syn/Makefile
@@ -1,5 +1,5 @@
 DESIGN_NAME := blink
-WORK_FILES   := ../rtl/blink.vhd
+WORK_FILES  := ../../lib/user_components.vhd ../rtl/blink.vhd
 GM_FILES    := ../../lib/rtl_components.vhd
 GHDL_FLAGS  := --std=08 --workdir=build -Pbuild
 YOSYSPIPE   := -nomx8 -luttree -retime
@@ -20,6 +20,7 @@ build/gatemate-obj08.cf: ${GM_FILES}
 	ghdl -a ${GHDL_FLAGS} --work=gatemate ${GM_FILES}
 
 ${DESIGN_NAME}.v: build/work-obj08.cf
+	ghdl --synth ${GHDL_FLAGS} ${DESIGN_NAME} > ${DESIGN_NAME}.vhd
 	yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \
 	  2>&1 | tee build/yosys-report.txt
 
@@ -34,4 +35,4 @@ prog: ${DESIGN_NAME}.bit
 
 clean :
 	echo "# Cleaning files"
-	rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}.bit
+	rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}.vhd ${DESIGN_NAME}.bit
diff --git a/lib/user_components.vhd b/lib/user_components.vhd
new file mode 100644
index 0000000..0f31cda
--- /dev/null
+++ b/lib/user_components.vhd
@@ -0,0 +1,40 @@
+library ieee ;
+use ieee.std_logic_1164.all;
+
+
+-- Async reset synchronizer circuit inspired from
+-- Chris Cummings SNUG 2002 paper
+--   Synchronous Resets? Asynchronous Resets? 
+--   I am so confused!
+--   How will I ever know which to use?
+
+entity reset_sync is
+generic (
+  POLARITY : std_logic := '0'
+);
+port (
+  clk_i : in  std_logic;
+  rst_i : in  std_logic;
+  rst_o : out std_logic
+);
+end entity;
+
+
+architecture sim of reset_sync is
+
+  signal s_rst_d : std_logic_vector(1 downto 0);
+
+begin
+
+  process (clk_i, rst_i) is
+  begin
+    if (rst_i = POLARITY) then
+      s_rst_d <= (others => POLARITY);
+    elsif (rising_edge(clk_i)) then
+      s_rst_d <= s_rst_d(0) & not POLARITY;
+    end if;
+  end process;
+
+  rst_o <= s_rst_d(1);
+
+end architecture;