diff --git a/neorv32_aes/rtl/neorv32_aes.vhd b/neorv32_aes/rtl/neorv32_aes.vhd
new file mode 100644
index 0000000..5885baa
--- /dev/null
+++ b/neorv32_aes/rtl/neorv32_aes.vhd
@@ -0,0 +1,119 @@
+-- #################################################################################################
+-- # << NEORV32 - Example setup including the bootloader, for the Gatemate (c) Eval Board >>       #
+-- # ********************************************************************************************* #
+-- # BSD 3-Clause License                                                                          #
+-- #                                                                                               #
+-- # Copyright (c) 2022, Torsten Meissner. All rights reserved.                                    #
+-- #                                                                                               #
+-- # Redistribution and use in source and binary forms, with or without modification, are          #
+-- # permitted provided that the following conditions are met:                                     #
+-- #                                                                                               #
+-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
+-- #    conditions and the following disclaimer.                                                   #
+-- #                                                                                               #
+-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
+-- #    conditions and the following disclaimer in the documentation and/or other materials        #
+-- #    provided with the distribution.                                                            #
+-- #                                                                                               #
+-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
+-- #    endorse or promote products derived from this software without specific prior written      #
+-- #    permission.                                                                                #
+-- #                                                                                               #
+-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
+-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
+-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
+-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
+-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
+-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
+-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
+-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
+-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
+-- # ********************************************************************************************* #
+-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
+-- #################################################################################################
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library gatemate;
+use gatemate.components.all;
+
+
+entity neorv32_aes is
+  port (
+    -- Clock and Reset inputs
+    clk_i     : in  std_logic;  -- 10 MHz clock
+    rst_n_i   : in  std_logic;  -- SW3 button
+    -- LED outputs
+    led_n_o   : out std_logic_vector(7 downto 0);
+    -- UART0
+    uart_rx_i : in  std_logic;  -- PMODA IO
+    uart_tx_o : out std_logic   -- PMODA IO
+  );
+end entity;
+
+architecture rtl of neorv32_aes is
+
+  -- configuration --
+  constant f_clock_c : natural := 26_000_000; -- clock frequency in Hz
+
+  -- Globals
+  signal s_pll_lock : std_logic;
+  signal s_pll_clk  : std_logic;
+  signal s_cfg_end  : std_logic;
+
+  signal s_rst_n : std_logic;
+
+  signal s_con_pwm : std_logic_vector(2 downto 0);
+  
+begin
+
+  PLL : CC_PLL
+  generic map (
+    REF_CLK => "10",
+    OUT_CLK => "26",
+    PERF_MD => "SPEED"
+  )
+  port map (
+    CLK_REF             => clk_i,
+    USR_CLK_REF         => '0',
+    CLK_FEEDBACK        => '0',
+    USR_LOCKED_STDY_RST => '0',
+    USR_PLL_LOCKED_STDY => open,
+    USR_PLL_LOCKED      => s_pll_lock,
+    CLK0                => s_pll_clk,
+    CLK90               => open,
+    CLK180              => open,
+    CLK270              => open,
+    CLK_REF_OUT         => open
+  );
+
+  cfg_end : CC_CFG_END
+  port map (
+    CFG_END => s_cfg_end
+  );
+
+  s_rst_n <= s_pll_lock and s_cfg_end and rst_n_i;
+
+  -- The core of the problem ----------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  neorv32_inst: entity work.neorv32_ProcessorTop_Minimal
+  generic map (
+    CLOCK_FREQUENCY => f_clock_c -- clock frequency of s_pll_clk in Hz
+  )
+  port map (
+    -- Global control --
+    clk_i  => std_ulogic(s_pll_clk),
+    rstn_i => std_ulogic(s_rst_n),
+	    -- PWM (to on-board RGB LED) --
+    pwm_o  => s_con_pwm
+  );
+
+  -- IO Connection --------------------------------------------------------------------------
+  -- -------------------------------------------------------------------------------------------
+  led_n_o(4 downto 0) <= (others => '1');
+  led_n_o(7 downto 5) <= s_con_pwm;
+  uart_tx_o <= uart_rx_i;
+
+end architecture;
diff --git a/neorv32_aes/syn/Makefile b/neorv32_aes/syn/Makefile
new file mode 100644
index 0000000..35cdfde
--- /dev/null
+++ b/neorv32_aes/syn/Makefile
@@ -0,0 +1,110 @@
+DESIGN_NAME := neorv32_aes
+
+NEORV32_CORE_DIR  := ../../neorv32/rtl/core
+NEORV32_PKG       := $(NEORV32_CORE_DIR)/neorv32_package.vhd
+NEORV32_APP_SRC   := $(NEORV32_CORE_DIR)/neorv32_application_image.vhd
+NEORV32_TEMPLATES := ../../neorv32/rtl/processor_templates
+
+NEORV32_MEM_ENTITIES := \
+  $(NEORV32_CORE_DIR)/neorv32_dmem.entity.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_imem.entity.vhd
+
+NEORV32_MEM_SRC := \
+  $(NEORV32_CORE_DIR)/mem/neorv32_imem.default.vhd \
+  $(NEORV32_CORE_DIR)/mem/neorv32_dmem.default.vhd
+
+NEORV32_CORE_SRC := \
+  $(NEORV32_CORE_DIR)/neorv32_bootloader_image.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_boot_rom.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_bus_keeper.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_busswitch.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cfs.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_alu.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_bus.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_control.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_cp_bitmanip.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_cp_cfu.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_cp_fpu.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_cp_muldiv.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_cp_shifter.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_decompressor.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_cpu_regfile.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_debug_dm.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_debug_dtm.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_fifo.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_gpio.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_gptmr.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_icache.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_mtime.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_neoled.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_onewire.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_pwm.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_slink.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_spi.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_sysinfo.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_top.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_trng.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_twi.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_uart.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_wdt.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_wishbone.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_xip.vhd \
+  $(NEORV32_CORE_DIR)/neorv32_xirq.vhd
+
+NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} \
+  ${NEORV32_MEM_SRC} ${NEORV32_CORE_SRC}
+
+WORK_FILES  := $(NEORV32_TEMPLATES)/neorv32_ProcessorTop_Minimal*.vhd ../rtl/${DESIGN_NAME}.vhd
+GM_FILES    := ../../lib/rtl_components.vhd
+
+GHDL_FLAGS  := --std=08 --workdir=build -Pbuild
+YOSYSPIPE   := -nomx8 -retime
+PNRFLAGS    := -om 3
+PNRTOOL     := $(shell which p_r)
+
+.PHONY: all syn imp prog syn_sim imp_sim
+
+all: imp
+syn: ${DESIGN_NAME}.v
+imp: ${DESIGN_NAME}.bit
+
+build/work-obj08.cf: ${WORK_FILES} build/gatemate-obj08.cf build/neorv32-obj08.cf
+	ghdl -a ${GHDL_FLAGS} --work=work ${WORK_FILES}
+
+build/neorv32-obj08.cf: build/gatemate-obj08.cf ${NEORV32_SRC}
+	ghdl -a $(GHDL_FLAGS) --work=neorv32 ${NEORV32_SRC}
+
+build/gatemate-obj08.cf: ${GM_FILES}
+	mkdir -p build
+	ghdl -a ${GHDL_FLAGS} --work=gatemate ${GM_FILES}
+
+# Synthesis target for implementation
+${DESIGN_NAME}.v: build/work-obj08.cf
+	yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --warn-no-binding --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \
+	  2>&1 | tee build/yosys-report.txt
+
+# Implementation target for FPGA
+${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf
+	cd build && \
+	  ${PNRTOOL} -i ../${DESIGN_NAME}.v -o $@ --ccf ../${DESIGN_NAME}.ccf $(PNRFLAGS) \
+	  2>&1 | tee p_r-report.txt && \
+	  mv ${DESIGN_NAME}*.bit ../$@
+
+# Post-synthesis simulation target
+syn_sim: ${DESIGN_NAME}.v
+	iverilog -g2012 -o tb_${DESIGN_NAME}_syn.vvp ${DESIGN_NAME}.v tb_${DESIGN_NAME}.v /usr/local/share/yosys/gatemate/cells_sim.v
+	vvp -N tb_${DESIGN_NAME}_syn.vvp -fst
+
+# Post-implementation simulation target
+imp_sim: ${DESIGN_NAME}.bit
+	iverilog -g2012 -o tb_${DESIGN_NAME}_imp.vvp build/${DESIGN_NAME}_00.v tb_${DESIGN_NAME}.v /opt/cc-toolchain-linux/bin/p_r/cpelib.v
+	vvp -N tb_${DESIGN_NAME}_imp.vvp -fst
+
+# FPGA FW load per JTAG
+prog: ${DESIGN_NAME}.bit
+	openFPGALoader -b gatemate_evb_jtag $<
+
+clean :
+	echo "# Cleaning files"
+	rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}_sim.v ${DESIGN_NAME}.vhd ${DESIGN_NAME}.bit *.vvp *.fst
diff --git a/neorv32_aes/syn/neorv32_aes.ccf b/neorv32_aes/syn/neorv32_aes.ccf
new file mode 100644
index 0000000..8ecaa91
--- /dev/null
+++ b/neorv32_aes/syn/neorv32_aes.ccf
@@ -0,0 +1,25 @@
+# Configuration for the Gatemate eval board
+
+Pin_in   "clk_i"   Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true;
+Pin_in   "rst_n_i" Loc = "IO_EB_B0"; # SW3
+
+Pin_out  "led_n_o[0]"  Loc = "IO_EB_B1"; # LED D1
+Pin_out  "led_n_o[1]"  Loc = "IO_EB_B2"; # LED D2
+Pin_out  "led_n_o[2]"  Loc = "IO_EB_B3"; # LED D3
+Pin_out  "led_n_o[3]"  Loc = "IO_EB_B4"; # LED D4
+Pin_out  "led_n_o[4]"  Loc = "IO_EB_B5"; # LED D5
+Pin_out  "led_n_o[5]"  Loc = "IO_EB_B6"; # LED D6
+Pin_out  "led_n_o[6]"  Loc = "IO_EB_B7"; # LED D7
+Pin_out  "led_n_o[7]"  Loc = "IO_EB_B8"; # LED D8
+
+Pin_in   "uart_rx_i"  Loc = "IO_NB_A1"; # PMODA IO3
+Pin_out  "uart_tx_o"  Loc = "IO_NB_A0"; # PMODA IO1
+
+Pin_out "debug_o[0]" Loc = "IO_NB_A4";
+Pin_out "debug_o[1]" Loc = "IO_NB_A5";
+Pin_out "debug_o[2]" Loc = "IO_NB_A6";
+Pin_out "debug_o[3]" Loc = "IO_NB_A7";
+Pin_out "debug_o[4]" Loc = "IO_NB_B4";
+Pin_out "debug_o[5]" Loc = "IO_NB_B5";
+Pin_out "debug_o[6]" Loc = "IO_NB_B6";
+Pin_out "debug_o[7]" Loc = "IO_NB_B7";