diff --git a/uart_loop/syn/tb_uart_loop.v b/uart_loop/syn/tb_uart_loop.v
index a4bb9b1..b248b08 100644
--- a/uart_loop/syn/tb_uart_loop.v
+++ b/uart_loop/syn/tb_uart_loop.v
@@ -54,6 +54,7 @@ module tb_uart_loop;
   // Testbench variables
   reg [7:0] tx_data = 8'h0;
   reg [7:0] rx_data = 8'h0;
+  reg [7:0] ref_data [0:15];
 
   // Testbench 1/2 clock period
   localparam clk_half_period = 50;
@@ -85,12 +86,13 @@ module tb_uart_loop;
     forever @(posedge rst_n) begin
     uart_rx = 1'b1;
     #uart_bit_period;
-    for (integer tx = 0; tx < 32; tx = tx + 1) begin
-      tx_data = tx;
+    for (integer i = 0; i < $size(ref_data); i = i + 1) begin
+      tx_data = {$random} % 255;
+      ref_data[i] = tx_data;
       $display ("UART send: 0x%h", tx_data);
       uart_rx = 1'b0;
       #uart_bit_period;
-      for (integer i = 0; i < 7; i = i + 1) begin
+      for (integer i = 0; i <= 7; i = i + 1) begin
         uart_rx = tx_data[i];
         #uart_bit_period;
       end
@@ -104,18 +106,18 @@ module tb_uart_loop;
   // Checker
   initial begin
     @(posedge rst_n)
-    for (reg [7:0] rx = 0; rx < 32; rx = rx + 1) begin
+    for (integer i = 0; i < $size(ref_data); i = i + 1) begin
       @(negedge uart_tx)
       #uart_bit_period;
       #uart_bit_half_period;
-      for (integer i = 0; i < 7; i = i + 1) begin
+      for (integer i = 0; i <= 7; i = i + 1) begin
         rx_data[i] = uart_tx;
         #uart_bit_period;
       end
-      assert (rx_data == rx)
+      assert (rx_data == ref_data[i])
         $display("UART recv: 0x%h", rx_data);
       else
-        $warning("UART receive error, got 0x%h, expected 0x%h", rx_data, rx);
+        $error("UART receive error, got 0x%h, expected 0x%h", rx_data, ref_data[i]);
     end
     $display ("UART tests finished");
     $finish;
diff --git a/uart_reg/syn/tb_uart_reg.v b/uart_reg/syn/tb_uart_reg.v
index 00b727e..694ca95 100644
--- a/uart_reg/syn/tb_uart_reg.v
+++ b/uart_reg/syn/tb_uart_reg.v
@@ -90,7 +90,7 @@ module tb_uart_reg;
       $display ("UART send: 0x%h", tx_data);
       uart_rx = 1'b0;
       #uart_bit_period;
-      for (integer i = 0; i < 7; i = i + 1) begin
+      for (integer i = 0; i <= 7; i = i + 1) begin
         uart_rx = tx_data[i];
         #uart_bit_period;
       end
@@ -108,7 +108,7 @@ module tb_uart_reg;
       @(negedge uart_tx)
       #uart_bit_period;
       #uart_bit_half_period;
-      for (integer i = 0; i < 7; i = i + 1) begin
+      for (integer i = 0; i <= 7; i = i + 1) begin
         rx_data[i] = uart_tx;
         #uart_bit_period;
       end
diff --git a/uart_trng/syn/tb_uart_trng.v b/uart_trng/syn/tb_uart_trng.v
index 00b727e..ba52f36 100644
--- a/uart_trng/syn/tb_uart_trng.v
+++ b/uart_trng/syn/tb_uart_trng.v
@@ -43,13 +43,12 @@ module CC_CFG_END (
 
 endmodule
 
-module tb_uart_reg;
+module tb_uart_trng;
 
   // DUT in/out
   reg  clk   = 1'b0;
   reg  rst_n = 1'b1;
-  reg  uart_rx;
-  wire uart_tx;
+  reg  uart_tx;
 
   // Testbench variables
   reg [7:0] tx_data = 8'h0;
@@ -62,17 +61,16 @@ module tb_uart_reg;
   localparam uart_bit_period = 1000000000 / 9600;
   localparam uart_bit_half_period = uart_bit_period/2;
 
-  uart_reg UUT (.clk_i(clk), .rst_n_i(rst_n), .uart_rx_i(uart_rx), .uart_tx_o(uart_tx));
+  uart_trng UUT (.clk_i(clk), .rst_n_i(rst_n), .uart_tx_o(uart_tx));
 
   // set dumpfile
   initial begin
-    $dumpfile ("tb_uart_reg.fst");
-    $dumpvars (0, tb_uart_reg);
+    $dumpfile ("tb_uart_trng.fst");
+    $dumpvars (0, tb_uart_trng);
   end
     
   // Setup simulation
   initial begin
-    uart_rx = 1'b1;
     #1   rst_n = 1'b0;
     #120 rst_n = 1'b1;
   end
@@ -80,27 +78,6 @@ module tb_uart_reg;
   // Generate 10 mhz clock
   always #clk_half_period clk = !clk;
 
-  // Stimuli generator
-  initial 
-    forever @(posedge rst_n) begin
-    uart_rx = 1'b1;
-    #uart_bit_period;
-    for (integer tx = 0; tx < 32; tx = tx + 1) begin
-      tx_data = tx;
-      $display ("UART send: 0x%h", tx_data);
-      uart_rx = 1'b0;
-      #uart_bit_period;
-      for (integer i = 0; i < 7; i = i + 1) begin
-        uart_rx = tx_data[i];
-        #uart_bit_period;
-      end
-      uart_rx = 1'b1;
-      #uart_bit_period;
-      #uart_bit_period
-      #uart_bit_period;
-    end
-  end
-
   // Checker
   initial begin
     @(posedge rst_n)
@@ -112,10 +89,7 @@ module tb_uart_reg;
         rx_data[i] = uart_tx;
         #uart_bit_period;
       end
-      assert (rx_data == rx)
-        $display("UART recv: 0x%h", rx_data);
-      else
-        $warning("UART receive error, got 0x%h, expected 0x%h", rx_data, rx);
+      $display ("UART recv: 0x%h", rx_data);
     end
     $display ("UART tests finished");
     $finish;