From 8cf0e6185c2c596f6a42f5287b608d4af9e0a841 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Thu, 29 Dec 2022 14:45:58 +0100 Subject: [PATCH] blink & uart_reg designs are working now * Yosys with -luttree option seems to generate Verilog netlist which GateMate p_r tool cannot handle correctly * If -luttree option is used you get bitfiles with nearly random behaviour * So, the Yosys -luttree option is removed to get correctly working designs, even that the GateMate documentation recommends to use the option * Result is a design with worse timing, but it's working as desired :) * Add targets to run post-synthesis & post-implementation simulations * Add Verilog test benches for post-syn/post-imp simulations * Remove debug code --- blink/rtl/blink.vhd | 39 +++++++++++++-- blink/sim/Makefile | 14 +++--- blink/sim/tb_blink.vhd | 3 ++ blink/syn/Makefile | 36 ++++++++++++-- blink/syn/blink.ccf | 9 ++++ blink/syn/tb_blink.v | 93 ++++++++++++++++++++++++++++++++++++ uart_reg/rtl/uart_reg.vhd | 21 ++------ uart_reg/sim/Makefile | 2 +- uart_reg/sim/tb_uart_reg.vhd | 5 +- uart_reg/syn/Makefile | 25 ++++++---- uart_reg/syn/tb_uart_reg.v | 87 +++++++++++++++++++++++++-------- uart_reg/syn/uart_reg.ccf | 13 ++--- 12 files changed, 272 insertions(+), 75 deletions(-) create mode 100644 blink/syn/tb_blink.v diff --git a/blink/rtl/blink.vhd b/blink/rtl/blink.vhd index 94a63f5..43e7f49 100644 --- a/blink/rtl/blink.vhd +++ b/blink/rtl/blink.vhd @@ -11,6 +11,9 @@ use gatemate.components.all; entity blink is +generic ( + SIM : natural := 0 +); port ( clk_i : in std_logic; -- 10 MHz clock rst_n_i : in std_logic; -- SW3 button @@ -21,14 +24,19 @@ end entity blink; architecture rtl of blink is + subtype t_clk_cnt is unsigned(19 downto 0); + signal s_clk_cnt : t_clk_cnt; + signal s_clk_cnt_end : t_clk_cnt; + signal s_pll_clk : std_logic; signal s_pll_lock : std_logic; - signal s_clk_cnt : unsigned(19 downto 0); signal s_clk_en : boolean; signal s_rst_n : std_logic; signal s_cfg_end : std_logic; + signal s_sys_rst_n : std_logic; + begin pll : CC_PLL @@ -56,18 +64,42 @@ begin CFG_END => s_cfg_end ); + -- This works s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end; + -- This doesn't work. + -- The reset module seems to be removed during Yosys flatten pass, even + -- when the output is connected with an output port, WHY does this happen? + -- 2.5. Executing FLATTEN pass (flatten design). + -- Deleting now unused module reset_sync_c4ea21bb365bbeeaf5f2c654883e56d11e43c44e. + -- + reset : entity work.reset_sync + generic map ( + POLARITY => '0' + ) + port map ( + clk_i => s_pll_clk, + rst_i => rst_n_i and s_pll_lock and s_cfg_end, + rst_o => s_sys_rst_n + ); + + s_clk_cnt_end <= 20x"FFFFF" when SIM = 0 else -- synthesis + 20x"000FF"; -- simulation + process (s_pll_clk, s_rst_n) is begin if (not s_rst_n) then s_clk_cnt <= (others => '0'); elsif (rising_edge(s_pll_clk)) then - s_clk_cnt <= s_clk_cnt + 1; + if (s_clk_cnt = s_clk_cnt_end) then + s_clk_cnt <= (others => '0'); + else + s_clk_cnt <= s_clk_cnt + 1; + end if; end if; end process; - s_clk_en <= s_clk_cnt = (s_clk_cnt'range => '1'); + s_clk_en <= s_clk_cnt = s_clk_cnt_end; process (s_pll_clk, s_rst_n) is begin @@ -80,4 +112,5 @@ begin end if; end process; + end architecture; diff --git a/blink/sim/Makefile b/blink/sim/Makefile index 8abb233..2c364d3 100644 --- a/blink/sim/Makefile +++ b/blink/sim/Makefile @@ -1,8 +1,8 @@ DESIGN_NAME := blink -LIB_SRC := ../../lib/components.vhd ../../lib/sim_components.vhd -RTL_SRC := ../rtl/${DESIGN_NAME}.vhd +LIB_SRC := ../../lib/rtl_components.vhd ../../lib/sim_components.vhd +RTL_SRC := ../../lib/user_components.vhd ../rtl/${DESIGN_NAME}.vhd SIM_SRC := tb_${DESIGN_NAME}.vhd -VHD_STD := 08 +SIM_FLAGS := --std=08 -fpsl --workdir=work .PHONY: all compile sim clean @@ -11,15 +11,15 @@ compile: tb_${DESIGN_NAME} tb_${DESIGN_NAME}: ${LIB_SRC} ${RTL_SRC} ${SIM_SRC} | work @echo "Analyze gatemate library ..." - ghdl -a --std=${VHD_STD} -fpsl --workdir=work --work=gatemate ${LIB_SRC} + ghdl -a ${SIM_FLAGS} --work=gatemate ${LIB_SRC} @echo "Analyze testbench & design ..." - ghdl -a --std=${VHD_STD} -fpsl --workdir=work -Pwork ${RTL_SRC} ${SIM_SRC} + ghdl -a ${SIM_FLAGS} -Pwork ${RTL_SRC} ${SIM_SRC} @echo "Elaborate testbench & design ..." - ghdl -e --std=${VHD_STD} -fpsl --workdir=work -Pwork $@ + ghdl -e ${SIM_FLAGS} -Pwork $@ sim: tb_${DESIGN_NAME} @echo "Run testbench ..." - ghdl -r tb_${DESIGN_NAME} --assert-level=error + ghdl -r ${SIM_FLAGS} -Pwork tb_${DESIGN_NAME} --assert-level=error --wave=tb_${DESIGN_NAME}.ghw work: mkdir $@ diff --git a/blink/sim/tb_blink.vhd b/blink/sim/tb_blink.vhd index c72c982..c8f3525 100644 --- a/blink/sim/tb_blink.vhd +++ b/blink/sim/tb_blink.vhd @@ -19,6 +19,9 @@ architecture sim of tb_blink is begin dut : entity work.blink + generic map ( + SIM => 1 + ) port map ( clk_i => s_clk, rst_n_i => s_rst_n, diff --git a/blink/syn/Makefile b/blink/syn/Makefile index c0c866e..7938605 100644 --- a/blink/syn/Makefile +++ b/blink/syn/Makefile @@ -2,11 +2,12 @@ DESIGN_NAME := blink WORK_FILES := ../../lib/user_components.vhd ../rtl/blink.vhd GM_FILES := ../../lib/rtl_components.vhd GHDL_FLAGS := --std=08 --workdir=build -Pbuild -YOSYSPIPE := -nomx8 -luttree -retime -PNRFLAGS := -sp off -om 2 -cCP on +YOSYSPIPE := -nomx8 -retime +# ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate? +PNRFLAGS := -om 2 PNRTOOL := $(shell which p_r) -.PHONY: all syn imp prog +.PHONY: all syn imp prog syn_sim imp_sim all: imp syn: ${DESIGN_NAME}.v @@ -19,20 +20,45 @@ build/gatemate-obj08.cf: ${GM_FILES} mkdir -p build ghdl -a ${GHDL_FLAGS} --work=gatemate ${GM_FILES} +# Synthesis target for implementation ${DESIGN_NAME}.v: build/work-obj08.cf ghdl --synth ${GHDL_FLAGS} ${DESIGN_NAME} > ${DESIGN_NAME}.vhd - yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \ + yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --warn-no-binding --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \ 2>&1 | tee build/yosys-report.txt +# Synthesis target for post-syn/post-imp simulation +${DESIGN_NAME}_sim.v: build/work-obj08.cf + ghdl --synth ${GHDL_FLAGS} ${DESIGN_NAME} > ${DESIGN_NAME}.vhd + yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} -gSIM=1 --warn-no-binding --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \ + 2>&1 | tee build/yosys-report.txt + +# Implementation target for FPGA ${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf cd build && \ ${PNRTOOL} -i ../${DESIGN_NAME}.v -o $@ --ccf ../${DESIGN_NAME}.ccf $(PNRFLAGS) \ 2>&1 | tee p_r-report.txt && \ mv ${DESIGN_NAME}*.bit ../$@ +# Implementation target for post-implementation simulation +build/${DESIGN_NAME}_00.v: ${DESIGN_NAME}_sim.v ${DESIGN_NAME}.ccf + cd build && \ + ${PNRTOOL} -i ../${DESIGN_NAME}_sim.v -o ${DESIGN_NAME}.v --ccf ../${DESIGN_NAME}.ccf $(PNRFLAGS) \ + 2>&1 | tee p_r-report.txt + +# Post-synthesis simulation target +syn_sim: ${DESIGN_NAME}_sim.v + iverilog -g2012 -o tb_${DESIGN_NAME}_syn.vvp ${DESIGN_NAME}_sim.v tb_${DESIGN_NAME}.v /usr/local/share/yosys/gatemate/cells_sim.v + vvp -N tb_${DESIGN_NAME}_syn.vvp -fst + +# Post-implementation simulation target +imp_sim: build/${DESIGN_NAME}_00.v + iverilog -g2012 -o tb_${DESIGN_NAME}_imp.vvp build/${DESIGN_NAME}_00.v tb_${DESIGN_NAME}.v /opt/cc-toolchain-linux/bin/p_r/cpelib.v + vvp -N tb_${DESIGN_NAME}_imp.vvp -fst + +# FPGA FW load per JTAG prog: ${DESIGN_NAME}.bit openFPGALoader -b gatemate_evb_jtag $< clean : echo "# Cleaning files" - rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}.vhd ${DESIGN_NAME}.bit + rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}_sim.v ${DESIGN_NAME}.vhd ${DESIGN_NAME}.bit *.vvp *.fst diff --git a/blink/syn/blink.ccf b/blink/syn/blink.ccf index f683ccf..de85d72 100644 --- a/blink/syn/blink.ccf +++ b/blink/syn/blink.ccf @@ -11,3 +11,12 @@ Pin_out "led_n_o[4]" Loc = "IO_EB_B5"; # LED D5 Pin_out "led_n_o[5]" Loc = "IO_EB_B6"; # LED D6 Pin_out "led_n_o[6]" Loc = "IO_EB_B7"; # LED D7 Pin_out "led_n_o[7]" Loc = "IO_EB_B8"; # LED D8 + +Pin_out "debug_o[0]" Loc = "IO_NB_A4"; +Pin_out "debug_o[1]" Loc = "IO_NB_A5"; +Pin_out "debug_o[2]" Loc = "IO_NB_A6"; +Pin_out "debug_o[3]" Loc = "IO_NB_A7"; +Pin_out "debug_o[4]" Loc = "IO_NB_B4"; +Pin_out "debug_o[5]" Loc = "IO_NB_B5"; +Pin_out "debug_o[6]" Loc = "IO_NB_B6"; +Pin_out "debug_o[7]" Loc = "IO_NB_B7"; diff --git a/blink/syn/tb_blink.v b/blink/syn/tb_blink.v new file mode 100644 index 0000000..75008db --- /dev/null +++ b/blink/syn/tb_blink.v @@ -0,0 +1,93 @@ +`timescale 1 ns/1 ns // time-unit = 1 ns, precision = 10 ps + +// simplified CC_PLL model +module CC_PLL #( + parameter REF_CLK = "", // e.g. "10.0" + parameter OUT_CLK = "", // e.g. "50.0" + parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED + parameter LOW_JITTER = 1, + parameter CI_FILTER_CONST = 2, + parameter CP_FILTER_CONST = 4 +)( + input CLK_REF, CLK_FEEDBACK, USR_CLK_REF, + input USR_LOCKED_STDY_RST, USR_SET_SEL, + output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED, + output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT +); + + reg r_pll_clk; + reg r_user_pll_locked; + + // OUT_FREQ = 2 MHz + integer clk_half_period = 250; + + initial begin + r_pll_clk = 1'b0; + r_user_pll_locked = 1'b1; + end + + always #clk_half_period r_pll_clk = ~r_pll_clk; + + assign CLK0 = r_pll_clk; + assign USR_PLL_LOCKED = r_user_pll_locked; + +endmodule + + +// simplified CC_CFG_END model +module CC_CFG_END ( + output CFG_END +); + + assign CFG_END = 1'b1; + +endmodule + + +module tb_blink; + + // DUT in/out + reg clk = 1'b0; + reg rst_n = 1'b1; + wire [7:0] led_n; + + // Testbench variables + reg [7:0] led_exp = 8'hfe; + + // Testbench 1/2 clock period + localparam clk_half_period = 50; + + blink DUT (.clk_i(clk), .rst_n_i(rst_n), .led_n_o(led_n)); + + // Set dumpfile + initial begin + $dumpfile ("tb_blink.fst"); + $dumpvars (0, tb_blink); + end + + // Setup simulation + initial begin + #1 rst_n = 1'b0; + #120 rst_n = 1'b1; + end + + // Generate 10 mhz clock + always #clk_half_period clk = !clk; + + // Checker + initial begin + @(posedge rst_n) + for (integer i = 0; i < 7; i = i + 1) begin + assert (led_n == led_exp) + $display("LED : 0x%h", led_n); + else + $warning("LED error, got 0x%h, expected 0x%h", led_n, led_exp); + #128_000; + led_exp = {led_exp[6:0], led_exp[7]}; + end + $display ("LED tests finished"); + $finish; + end + + +endmodule diff --git a/uart_reg/rtl/uart_reg.vhd b/uart_reg/rtl/uart_reg.vhd index 6b9ee03..dc31c5d 100644 --- a/uart_reg/rtl/uart_reg.vhd +++ b/uart_reg/rtl/uart_reg.vhd @@ -1,5 +1,4 @@ --- This design should display incrementing binary numbers --- at LED1-LED8 of the GateMate FPGA Starter Kit. +-- This design implements a simple UART loop with 9600 baud library ieee ; @@ -12,12 +11,10 @@ use gatemate.components.all; entity uart_reg is port ( - clk_i : in std_logic; -- 10 MHz clock - rst_n_i : in std_logic; -- SW3 button - uart_rx_i : in std_logic; - uart_tx_o : out std_logic; - led_n_o : out std_logic_vector(3 downto 0); -- LED1..LED2 - debug_o : out std_logic_vector(3 downto 0) + clk_i : in std_logic; -- 10 MHz clock + rst_n_i : in std_logic; -- SW3 button + uart_rx_i : in std_logic; -- PMODA IO3 + uart_tx_o : out std_logic -- PMODA IO5 ); end entity uart_reg; @@ -26,7 +23,6 @@ architecture rtl of uart_reg is signal s_pll_clk : std_logic; signal s_pll_lock : std_logic; - signal s_clk_en : boolean; signal s_rst_n : std_logic; signal s_cfg_end : std_logic; @@ -34,7 +30,6 @@ architecture rtl of uart_reg is signal s_uart_rx_tdata : std_logic_vector(7 downto 0); signal s_uart_rx_tvalid : std_logic; signal s_uart_rx_tready : std_logic; - signal s_uart_tx : std_logic; begin @@ -97,10 +92,4 @@ begin s_rst_n <= rst_n_i and s_pll_lock and s_cfg_end; - -- Start with simple loop --- uart_tx_o <= uart_rx_i; - - -- Debug output - led_n_o <= uart_rx_i & s_rst_n & not (s_pll_lock, s_cfg_end); - end architecture; diff --git a/uart_reg/sim/Makefile b/uart_reg/sim/Makefile index 664b36d..3ee810a 100644 --- a/uart_reg/sim/Makefile +++ b/uart_reg/sim/Makefile @@ -1,5 +1,5 @@ DESIGN_NAME := uart_reg -LIB_SRC := ../../lib/components.vhd ../../lib/sim_components.vhd +LIB_SRC := ../../lib/rtl_components.vhd ../../lib/sim_components.vhd RTL_SRC := ../rtl/uart_tx.vhd ../rtl/uart_rx.vhd ../rtl/${DESIGN_NAME}.vhd SIM_SRC := tb_${DESIGN_NAME}.vhd SIM_FLAGS := --std=08 -fpsl --workdir=work diff --git a/uart_reg/sim/tb_uart_reg.vhd b/uart_reg/sim/tb_uart_reg.vhd index d19c85d..6af49dc 100644 --- a/uart_reg/sim/tb_uart_reg.vhd +++ b/uart_reg/sim/tb_uart_reg.vhd @@ -14,8 +14,6 @@ architecture sim of tb_uart_reg is signal s_clk : std_logic := '1'; signal s_rst_n : std_logic := '0'; - signal s_led_n : std_logic_vector(3 downto 0); - signal s_uart_rx : std_logic := '1'; signal s_uart_tx : std_logic; @@ -29,8 +27,7 @@ begin clk_i => s_clk, rst_n_i => s_rst_n, uart_rx_i => s_uart_rx, - uart_tx_o => s_uart_tx, - led_n_o => s_led_n + uart_tx_o => s_uart_tx ); s_rst_n <= '1' after 120 ns; diff --git a/uart_reg/syn/Makefile b/uart_reg/syn/Makefile index 105ff07..96dae39 100644 --- a/uart_reg/syn/Makefile +++ b/uart_reg/syn/Makefile @@ -2,11 +2,12 @@ DESIGN_NAME := uart_reg WORK_FILES := ../rtl/uart_tx.vhd ../rtl/uart_rx.vhd ../rtl/uart_reg.vhd GM_FILES := ../../lib/rtl_components.vhd GHDL_FLAGS := --std=08 --workdir=build -Pbuild -YOSYSPIPE := -nomx8 -luttree -retime -PNRFLAGS := -sp off -om 2 -cCP on +YOSYSPIPE := -nomx8 -retime +# ATTENTION: -luttree option seems to mis-synthesize the design, broken with synth_gatemate? +PNRFLAGS := -om 2 PNRTOOL := $(shell which p_r) -.PHONY: all syn imp prog +.PHONY: all syn imp prog syn_sim imp_sim all: imp syn: ${DESIGN_NAME}.v @@ -19,27 +20,33 @@ build/gatemate-obj08.cf: ${GM_FILES} mkdir -p build ghdl -a ${GHDL_FLAGS} --work=gatemate ${GM_FILES} +# Synthesis target for implementation ${DESIGN_NAME}.v: build/work-obj08.cf - yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \ + ghdl --synth ${GHDL_FLAGS} ${DESIGN_NAME} > ${DESIGN_NAME}.vhd + yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --warn-no-binding --no-formal ${DESIGN_NAME}; synth_gatemate -top $(DESIGN_NAME) ${YOSYSPIPE} -vlog $@' \ 2>&1 | tee build/yosys-report.txt -build/${DESIGN_NAME}_00.v ${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf +# Implementation target for FPGA +${DESIGN_NAME}.bit: ${DESIGN_NAME}.v ${DESIGN_NAME}.ccf cd build && \ - ${PNRTOOL} -i ../${DESIGN_NAME}.v -o ${DESIGN_NAME}.bit --ccf ../${DESIGN_NAME}.ccf $(PNRFLAGS) \ + ${PNRTOOL} -i ../${DESIGN_NAME}.v -o $@ --ccf ../${DESIGN_NAME}.ccf $(PNRFLAGS) \ 2>&1 | tee p_r-report.txt && \ - mv ${DESIGN_NAME}*.bit ../${DESIGN_NAME}.bit + mv ${DESIGN_NAME}*.bit ../$@ +# Post-synthesis simulation target syn_sim: ${DESIGN_NAME}.v iverilog -g2012 -o tb_${DESIGN_NAME}_syn.vvp ${DESIGN_NAME}.v tb_${DESIGN_NAME}.v /usr/local/share/yosys/gatemate/cells_sim.v vvp -N tb_${DESIGN_NAME}_syn.vvp -fst -imp_sim: build/${DESIGN_NAME}_00.v +# Post-implementation simulation target +imp_sim: ${DESIGN_NAME}.bit iverilog -g2012 -o tb_${DESIGN_NAME}_imp.vvp build/${DESIGN_NAME}_00.v tb_${DESIGN_NAME}.v /opt/cc-toolchain-linux/bin/p_r/cpelib.v vvp -N tb_${DESIGN_NAME}_imp.vvp -fst +# FPGA FW load per JTAG prog: ${DESIGN_NAME}.bit openFPGALoader -b gatemate_evb_jtag $< clean : echo "# Cleaning files" - rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}.bit *.vvp *.fst + rm -rf build ${DESIGN_NAME}.v ${DESIGN_NAME}_sim.v ${DESIGN_NAME}.vhd ${DESIGN_NAME}.bit *.vvp *.fst diff --git a/uart_reg/syn/tb_uart_reg.v b/uart_reg/syn/tb_uart_reg.v index 4057240..9756226 100644 --- a/uart_reg/syn/tb_uart_reg.v +++ b/uart_reg/syn/tb_uart_reg.v @@ -1,20 +1,68 @@ `timescale 1 ns/10 ps // time-unit = 1 ns, precision = 10 ps +// simplified CC_PLL model +module CC_PLL #( + parameter REF_CLK = "", // e.g. "10.0" + parameter OUT_CLK = "", // e.g. "50.0" + parameter PERF_MD = "", // LOWPOWER, ECONOMY, SPEED + parameter LOW_JITTER = 1, + parameter CI_FILTER_CONST = 2, + parameter CP_FILTER_CONST = 4 +)( + input CLK_REF, CLK_FEEDBACK, USR_CLK_REF, + input USR_LOCKED_STDY_RST, USR_SET_SEL, + output USR_PLL_LOCKED_STDY, USR_PLL_LOCKED, + output CLK270, CLK180, CLK90, CLK0, CLK_REF_OUT +); + + reg r_pll_clk; + reg r_user_pll_locked; + + // OUT_FREQ = 1 MHz + integer clk_half_period = 500; + + initial begin + r_pll_clk = 1'b0; + r_user_pll_locked = 1'b1; + end + + always #clk_half_period r_pll_clk = ~r_pll_clk; + + assign CLK0 = r_pll_clk; + assign USR_PLL_LOCKED = r_user_pll_locked; + +endmodule + + +// simplified CC_CFG_END model +module CC_CFG_END ( + output CFG_END +); + + assign CFG_END = 1'b1; + +endmodule + module tb_uart_reg; - reg clk = 0; - reg rst_n; - reg uart_rx; + // DUT in/out + reg clk = 1'b0; + reg rst_n = 1'b1; + reg uart_rx; wire uart_tx; - reg [7:0] tx_data = 0; - reg [7:0] rx_data = 0; - wire [3:0] led_n; - localparam clk_half_period = 50; + // Testbench variables + reg [7:0] tx_data = 8'h0; + reg [7:0] rx_data = 8'h0; + + // Testbench 1/2 clock period + localparam clk_half_period = 50; + + // UART period calculation (9600 baud) localparam uart_bit_period = 1000000000 / 9600; localparam uart_bit_half_period = uart_bit_period/2; - uart_reg UUT (.clk_i(clk), .rst_n_i(rst_n), .uart_rx_i(uart_rx), .uart_tx_o(uart_tx), .led_n_o(led_n)); + uart_reg UUT (.clk_i(clk), .rst_n_i(rst_n), .uart_rx_i(uart_rx), .uart_tx_o(uart_tx)); // set dumpfile initial begin @@ -22,25 +70,22 @@ module tb_uart_reg; $dumpvars (0, tb_uart_reg); end - // setup simulation + // Setup simulation initial begin - rst_n = 1; - #1 rst_n = 0; - #20 rst_n = 1; + uart_rx = 1'b1; + #1 rst_n = 1'b0; + #120 rst_n = 1'b1; end - // generate clock with 100 mhz + // Generate 10 mhz clock always #clk_half_period clk = !clk; - initial begin - uart_rx = 1'b1; - end - + // Stimuli generator initial forever @(posedge rst_n) begin uart_rx = 1'b1; #uart_bit_period; - for (integer tx = 0; tx < 16; tx = tx + 1) begin + for (integer tx = 0; tx < 32; tx = tx + 1) begin tx_data = tx; $display ("UART send: 0x%h", tx_data); uart_rx = 1'b0; @@ -57,9 +102,9 @@ module tb_uart_reg; end // Checker - always begin - wait (rst_n) - for (reg [7:0] rx = 0; rx < 16; rx = rx + 1) begin + initial begin + @(posedge rst_n) + for (reg [7:0] rx = 0; rx < 32; rx = rx + 1) begin @(negedge uart_tx) #uart_bit_period; #uart_bit_half_period; diff --git a/uart_reg/syn/uart_reg.ccf b/uart_reg/syn/uart_reg.ccf index 0209c49..05bd5a5 100644 --- a/uart_reg/syn/uart_reg.ccf +++ b/uart_reg/syn/uart_reg.ccf @@ -3,15 +3,6 @@ Pin_in "clk_i" Loc = "IO_SB_A8" | SCHMITT_TRIGGER=true; Pin_in "rst_n_i" Loc = "IO_EB_B0"; # SW3 -Pin_out "led_n_o[0]" Loc = "IO_EB_B1"; # LED D1 -Pin_out "led_n_o[1]" Loc = "IO_EB_B2"; # LED D2 -Pin_out "led_n_o[2]" Loc = "IO_EB_B3"; # LED D3 -Pin_out "led_n_o[3]" Loc = "IO_EB_B4"; # LED D4 -#Pin_out "led_n_o[4]" Loc = "IO_EB_B5"; # LED D5 -#Pin_out "led_n_o[5]" Loc = "IO_EB_B6"; # LED D6 -#Pin_out "led_n_o[6]" Loc = "IO_EB_B7"; # LED D7 -#Pin_out "led_n_o[7]" Loc = "IO_EB_B8"; # LED D8 - Pin_in "uart_rx_i" Loc = "IO_NB_A1"; # PMODA IO3 Pin_out "uart_tx_o" Loc = "IO_NB_A2"; # PMODA IO5 @@ -19,3 +10,7 @@ Pin_out "debug_o[0]" Loc = "IO_NB_A4"; Pin_out "debug_o[1]" Loc = "IO_NB_A5"; Pin_out "debug_o[2]" Loc = "IO_NB_A6"; Pin_out "debug_o[3]" Loc = "IO_NB_A7"; +Pin_out "debug_o[4]" Loc = "IO_NB_B4"; +Pin_out "debug_o[5]" Loc = "IO_NB_B5"; +Pin_out "debug_o[6]" Loc = "IO_NB_B6"; +Pin_out "debug_o[7]" Loc = "IO_NB_B7";