diff --git a/blink/rtl/blink.vhd b/blink/rtl/blink.vhd index 1703747..6098dcb 100644 --- a/blink/rtl/blink.vhd +++ b/blink/rtl/blink.vhd @@ -6,6 +6,9 @@ library ieee ; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +library gatemate; +use gatemate.components.all; + entity blink is port ( @@ -18,14 +21,36 @@ end entity blink; architecture rtl of blink is - signal s_clk_cnt : unsigned(19 downto 0); - signal s_clk_en : boolean; + signal s_pll_clk : std_logic; + signal s_pll_lock : std_logic; + signal s_clk_cnt : unsigned(19 downto 0); + signal s_clk_en : boolean; signal s_led : unsigned(led_n_o'range); begin - process (clk_i, rst_n_i) is + pll : CC_PLL + generic map ( + REF_CLK => "10", + OUT_CLK => "1", + PERF_MD => "SPEED" + ) + port map ( + CLK_REF => clk_i, + CLK_FEEDBACK => '0', + USR_CLK_REF => '0', + USR_LOCKED_STDY_RST => not rst_n_i, + USR_PLL_LOCKED_STDY => open, + USR_PLL_LOCKED => s_pll_lock, + CLK270 => open, + CLK180 => open, + CLK0 => open, + CLK90 => open, + CLK_REF_OUT => s_pll_clk + ); + + process (s_pll_clk, rst_n_i) is begin if (not rst_n_i) then s_clk_cnt <= (others => '0'); @@ -36,7 +61,7 @@ begin s_clk_en <= s_clk_cnt = (s_clk_cnt'range => '1'); - process (clk_i, rst_n_i) is + process (s_pll_clk, rst_n_i) is begin if (not rst_n_i) then s_led <= (others => '0'); diff --git a/blink/syn/Makefile b/blink/syn/Makefile index a7ab675..d44abea 100644 --- a/blink/syn/Makefile +++ b/blink/syn/Makefile @@ -1,21 +1,23 @@ DESIGN_NAME := blink -SRC_FILES := ../rtl/blink.vhd -VHD_STD := 08 +WORK_FILES := ../rtl/blink.vhd +GM_FILES := ../../lib/components.vhd +GHDL_FLAGS := --std=08 --workdir=build -Pbuild .PHONY: all syn -all: ${DESIGN_NAME}_synth.vhd syn +all: syn syn: ${DESIGN_NAME}.v -${DESIGN_NAME}.o: ${SRC_FILES} - ghdl -a --std=${VHD_STD} ${SRC_FILES} +work-obj08.cf: ${WORK_FILES} gatemate-obj08.cf + ghdl -a ${GHDL_FLAGS} --work=work ${WORK_FILES} -${DESIGN_NAME}_synth.vhd: ${SRC_FILES} - ghdl --synth --std=$(VHD_STD) ${SRC_FILES} -e ${DESIGN_NAME} > $@ +gatemate-obj08.cf: ${GM_FILES} + mkdir -p build + ghdl -a ${GHDL_FLAGS} --work=gatemate ${GM_FILES} -${DESIGN_NAME}.v: ${DESIGN_NAME}.o - yosys -m ghdl -p 'ghdl --std=${VHD_STD} --no-formal ${DESIGN_NAME}; synth_gatemate -nomx8 -vlog $@' +${DESIGN_NAME}.v: work-obj08.cf + yosys -m ghdl -p 'ghdl ${GHDL_FLAGS} --no-formal ${DESIGN_NAME}; synth_gatemate -nomx8 -vlog $@' 2>&1 | tee build/yosys-report.txt clean : echo "# Cleaning files" - rm -f *.o work*.cf ${DESIGN_NAME}.v ${DESIGN_NAME}_synth.vhd + rm -rf build ${DESIGN_NAME}.v