diff --git a/neorv32_aes/rtl/neorv32_ProcessorTop_MinimalUart.vhd b/neorv32_aes/rtl/neorv32_ProcessorTop_MinimalUart.vhd new file mode 100644 index 0000000..412383e --- /dev/null +++ b/neorv32_aes/rtl/neorv32_ProcessorTop_MinimalUart.vhd @@ -0,0 +1,259 @@ +-- ################################################################################################# +-- # << NEORV32 - Minimal setup without a bootloader bur UART0 enabled >> # +-- # ********************************************************************************************* # +-- # BSD 3-Clause License # +-- # # +-- # Copyright (c) 2022, Torsten Meissner. All rights reserved. # +-- # # +-- # Redistribution and use in source and binary forms, with or without modification, are # +-- # permitted provided that the following conditions are met: # +-- # # +-- # 1. Redistributions of source code must retain the above copyright notice, this list of # +-- # conditions and the following disclaimer. # +-- # # +-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # +-- # conditions and the following disclaimer in the documentation and/or other materials # +-- # provided with the distribution. # +-- # # +-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # +-- # endorse or promote products derived from this software without specific prior written # +-- # permission. # +-- # # +-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # +-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # +-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # +-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # +-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # +-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # +-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # +-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # +-- # OF THE POSSIBILITY OF SUCH DAMAGE. # +-- # ********************************************************************************************* # +-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # +-- ################################################################################################# + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library neorv32; + +entity neorv32_top is + generic ( + CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz + HW_THREAD_ID : natural := 0; -- hardware thread id (32-bit) + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension? + CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M : boolean := false; -- implement mul/div extension? + CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx : boolean := false; -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system? + CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.? + + -- Extension Options -- + FAST_MUL_EN : boolean := false; -- use DSPs for M extension's multiplier + FAST_SHIFT_EN : boolean := false; -- use barrel shifter for shift operations + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS : natural := 0; -- number of regions (0..16) + PMP_MIN_GRANULARITY : natural := 4; -- minimal region granularity in bytes, has to be a power of 2, min 4 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS : natural := 0; -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH : natural := 40; -- total size of HPM counters (0..64) + + -- Internal Instruction memory -- + MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes + + -- Internal Data memory -- + MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory + MEM_INT_DMEM_SIZE : natural := 64*1024; -- size of processor-internal data memory in bytes + + -- Internal Cache memory -- + ICACHE_EN : boolean := false; -- implement instruction cache + ICACHE_NUM_BLOCKS : natural := 4; -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE : natural := 64; -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY : natural := 1; -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- Processor peripherals -- + IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)? + IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_PWM_NUM_CH : natural := 3; -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)? + IO_TRNG_EN : boolean := true; -- implement true random number generator (TRNG)? + IO_CFS_EN : boolean := true -- implement custom functions subsystem (CFS)? + ); + port ( + clk_i : in std_logic; + rstn_i : in std_logic; + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o : out std_ulogic_vector(3 downto 0); + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart_txd_o : out std_ulogic; -- UART0 send data + uart_rxd_i : in std_ulogic := '0' -- UART0 receive data + ); +end entity; + +architecture rtl of neorv32_top is + + -- internal IO connection -- + signal con_gpio_o : std_ulogic_vector(63 downto 0); + signal con_pwm_o : std_ulogic_vector(59 downto 0); + +begin + + -- IO Connection -------------------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + + -- GPIO -- + gpio_o <= con_gpio_o(3 downto 0); + + -- The core of the problem ---------------------------------------------------------------- + -- ------------------------------------------------------------------------------------------- + neorv32_inst: entity neorv32.neorv32_top + generic map ( + -- General -- + CLOCK_FREQUENCY => CLOCK_FREQUENCY, -- clock frequency of clk_i in Hz + INT_BOOTLOADER_EN => false, -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM + HW_THREAD_ID => HW_THREAD_ID, -- hardware thread id (32-bit) + + -- On-Chip Debugger (OCD) -- + ON_CHIP_DEBUGGER_EN => false, -- implement on-chip debugger? + + -- RISC-V CPU Extensions -- + CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension? + CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension? + CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement mul/div extension? + CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension? + CPU_EXTENSION_RISCV_Zfinx => CPU_EXTENSION_RISCV_Zfinx, -- implement 32-bit floating-point extension (using INT regs!) + CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system? + CPU_EXTENSION_RISCV_Zicntr => true, -- implement base counters? + CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.? + + -- Extension Options -- + FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier + FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations + + -- Physical Memory Protection (PMP) -- + PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (0..16) + PMP_MIN_GRANULARITY => PMP_MIN_GRANULARITY, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes + + -- Hardware Performance Monitors (HPM) -- + HPM_NUM_CNTS => HPM_NUM_CNTS, -- number of implemented HPM counters (0..29) + HPM_CNT_WIDTH => HPM_CNT_WIDTH, -- total size of HPM counters (1..64) + + -- Internal Instruction memory -- + MEM_INT_IMEM_EN => MEM_INT_IMEM_EN, -- implement processor-internal instruction memory + MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes + + -- Internal Data memory -- + MEM_INT_DMEM_EN => MEM_INT_DMEM_EN, -- implement processor-internal data memory + MEM_INT_DMEM_SIZE => MEM_INT_DMEM_SIZE, -- size of processor-internal data memory in bytes + + -- Internal Cache memory -- + ICACHE_EN => ICACHE_EN, -- implement instruction cache + ICACHE_NUM_BLOCKS => ICACHE_NUM_BLOCKS, -- i-cache: number of blocks (min 1), has to be a power of 2 + ICACHE_BLOCK_SIZE => ICACHE_BLOCK_SIZE, -- i-cache: block size in bytes (min 4), has to be a power of 2 + ICACHE_ASSOCIATIVITY => ICACHE_ASSOCIATIVITY, -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2 + + -- External memory interface -- + MEM_EXT_EN => false, -- implement external memory bus interface? + MEM_EXT_TIMEOUT => 0, -- cycles after a pending bus access auto-terminates (0 = disabled) + + -- Processor peripherals -- + IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)? + IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)? + IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)? + IO_UART1_EN => false, -- implement secondary universal asynchronous receiver/transmitter (UART1)? + IO_SPI_EN => false, -- implement serial peripheral interface (SPI)? + IO_TWI_EN => false, -- implement two-wire interface (TWI)? + IO_PWM_NUM_CH => 0, -- number of PWM channels to implement (0..60); 0 = disabled + IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)? + IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)? + IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)? + IO_CFS_CONFIG => x"00000000", -- custom CFS configuration generic + IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits + IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits + IO_NEOLED_EN => false -- implement NeoPixel-compatible smart LED interface (NEOLED)? + ) + port map ( + -- Global control -- + clk_i => clk_i, -- global clock, rising edge + rstn_i => rstn_i, -- global reset, low-active, async + + -- JTAG on-chip debugger interface (available if ON_CHIP_DEBUGGER_EN = true) -- + jtag_trst_i => '0', -- low-active TAP reset (optional) + jtag_tck_i => '0', -- serial clock + jtag_tdi_i => '0', -- serial data input + jtag_tdo_o => open, -- serial data output + jtag_tms_i => '0', -- mode select + + -- Wishbone bus interface (available if MEM_EXT_EN = true) -- + wb_tag_o => open, -- request tag + wb_adr_o => open, -- address + wb_dat_i => (others => '0'), -- read data + wb_dat_o => open, -- write data + wb_we_o => open, -- read/write + wb_sel_o => open, -- byte enable + wb_stb_o => open, -- strobe + wb_cyc_o => open, -- valid cycle + wb_ack_i => '0', -- transfer acknowledge + wb_err_i => '0', -- transfer error + + -- Advanced memory control signals (available if MEM_EXT_EN = true) -- + fence_o => open, -- indicates an executed FENCE operation + fencei_o => open, -- indicates an executed FENCEI operation + + -- GPIO (available if IO_GPIO_EN = true) -- + gpio_o => con_gpio_o, -- parallel output + gpio_i => (others => '0'), -- parallel input + + -- primary UART0 (available if IO_UART0_EN = true) -- + uart0_txd_o => uart_txd_o, -- UART0 send data + uart0_rxd_i => uart_rxd_i, -- UART0 receive data + uart0_rts_o => open, -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional + uart0_cts_i => '0', -- hw flow control: UART0.TX allowed to transmit, low-active, optional + + -- secondary UART1 (available if IO_UART1_EN = true) -- + uart1_txd_o => open, -- UART1 send data + uart1_rxd_i => '0', -- UART1 receive data + uart1_rts_o => open, -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional + uart1_cts_i => '0', -- hw flow control: UART1.TX allowed to transmit, low-active, optional + + -- SPI (available if IO_SPI_EN = true) -- + spi_sck_o => open, -- SPI serial clock + spi_sdo_o => open, -- controller data out, peripheral data in + spi_sdi_i => '0', -- controller data in, peripheral data out + spi_csn_o => open, -- SPI CS + + -- TWI (available if IO_TWI_EN = true) -- + twi_sda_io => open, -- twi serial data line + twi_scl_io => open, -- twi serial clock line + + -- PWM (available if IO_PWM_NUM_CH > 0) -- + pwm_o => open, -- pwm channels + + -- Custom Functions Subsystem IO -- + cfs_in_i => (others => '0'), -- custom CFS inputs conduit + cfs_out_o => open, -- custom CFS outputs conduit + + -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) -- + neoled_o => open, -- async serial data line + + -- System time -- + mtime_i => (others => '0'), -- current system time from ext. MTIME (if IO_MTIME_EN = false) + mtime_o => open, -- current system time from int. MTIME (if IO_MTIME_EN = true) + + -- Interrupts -- + mtime_irq_i => '0', -- machine timer interrupt, available if IO_MTIME_EN = false + msw_irq_i => '0', -- machine software interrupt + mext_irq_i => '0' -- machine external interrupt + ); + +end architecture; diff --git a/neorv32_aes/rtl/neorv32_aes.vhd b/neorv32_aes/rtl/neorv32_aes.vhd index 5885baa..131a492 100644 --- a/neorv32_aes/rtl/neorv32_aes.vhd +++ b/neorv32_aes/rtl/neorv32_aes.vhd @@ -56,7 +56,7 @@ end entity; architecture rtl of neorv32_aes is -- configuration -- - constant f_clock_c : natural := 26_000_000; -- clock frequency in Hz + constant f_clock_c : natural := 20_000_000; -- clock frequency in Hz -- Globals signal s_pll_lock : std_logic; @@ -65,14 +65,14 @@ architecture rtl of neorv32_aes is signal s_rst_n : std_logic; - signal s_con_pwm : std_logic_vector(2 downto 0); + signal s_con_gpio : std_logic_vector(3 downto 0); begin PLL : CC_PLL generic map ( REF_CLK => "10", - OUT_CLK => "26", + OUT_CLK => "20", PERF_MD => "SPEED" ) port map ( @@ -98,22 +98,41 @@ begin -- The core of the problem ---------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - neorv32_inst: entity work.neorv32_ProcessorTop_Minimal + neorv32_inst: entity work.neorv32_top generic map ( - CLOCK_FREQUENCY => f_clock_c -- clock frequency of s_pll_clk in Hz + CLOCK_FREQUENCY => f_clock_c, -- clock frequency of s_pll_clk in Hz + CPU_EXTENSION_RISCV_M => true, + FAST_MUL_EN => false, + FAST_SHIFT_EN => false, + MEM_INT_IMEM_SIZE => 8*1024, + MEM_INT_DMEM_SIZE => 16*1024, + IO_MTIME_EN => false, + IO_WDT_EN => false, + IO_TRNG_EN => false, + IO_CFS_EN => true ) port map ( -- Global control -- clk_i => std_ulogic(s_pll_clk), rstn_i => std_ulogic(s_rst_n), - -- PWM (to on-board RGB LED) -- - pwm_o => s_con_pwm + -- GPIO + gpio_o => s_con_gpio, + -- primary UART0 + uart_txd_o => uart_tx_o, + uart_rxd_i => uart_rx_i ); + -- p_r ERROR when connecting uart_rx_i & yosys option -retime (with both Yosys inferred & instantiated CC_BRAM_40K or CC_BRAM_40K memory) + -- FATAL ERROR: RAM 4070 Output DOA[6] not used but Input DIA[6] used! + -- program finished with exit code: 2 + + -- p_r ERROR with FAST_MUL_EN (even with the suggested p_r option sitched off) + -- FATAL ERROR: CP-lines in Multiplier cannot be used for CLK; please switch off using CP-lines for CLK (-cCP) + -- IO Connection -------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - led_n_o(4 downto 0) <= (others => '1'); - led_n_o(7 downto 5) <= s_con_pwm; - uart_tx_o <= uart_rx_i; + led_n_o(3 downto 0) <= s_con_gpio; + led_n_o(7 downto 4) <= (others => '1'); +-- uart_tx_o <= uart_rx_i; end architecture; diff --git a/neorv32_aes/syn/Makefile b/neorv32_aes/syn/Makefile index 35cdfde..f31fc8b 100644 --- a/neorv32_aes/syn/Makefile +++ b/neorv32_aes/syn/Makefile @@ -55,11 +55,12 @@ NEORV32_CORE_SRC := \ NEORV32_SRC := ${NEORV32_PKG} ${NEORV32_APP_SRC} ${NEORV32_MEM_ENTITIES} \ ${NEORV32_MEM_SRC} ${NEORV32_CORE_SRC} -WORK_FILES := $(NEORV32_TEMPLATES)/neorv32_ProcessorTop_Minimal*.vhd ../rtl/${DESIGN_NAME}.vhd +WORK_FILES := ../rtl/neorv32_ProcessorTop_MinimalUart.vhd ../rtl/${DESIGN_NAME}.vhd GM_FILES := ../../lib/rtl_components.vhd GHDL_FLAGS := --std=08 --workdir=build -Pbuild -YOSYSPIPE := -nomx8 -retime +YOSYSPIPE := -nomx8 +# -retime -cCP off PNRFLAGS := -om 3 PNRTOOL := $(shell which p_r)