From 9a275eeaa5e179256d57c2b763464c2b61630b67 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Thu, 29 Dec 2022 17:41:15 +0100 Subject: [PATCH] Update README --- README.md | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 72a06d6..923e947 100644 --- a/README.md +++ b/README.md @@ -6,7 +6,17 @@ Ongoing experiments with the Cologne Chip's GateMate FPGA architecture. All expe ### blink -Simple design which should display incrementing binary numbers with LED1-LED8 of the GateMate FPGA Starter Kit. It uses *CC_PLL* & *CC_CFG_END* primitives of the GateMate FPGA. +Simple design which should display a blinking LED waving from LED1-LED8 of the GateMate FPGA Starter Kit. It uses *CC_PLL* & *CC_CFG_END* primitives of the GateMate FPGA. + +### uart_reg + +Register file which can be accessed through UART. It uses *CC_PLL* & *CC_CFG_END* primitives of the GateMate FPGA. It contains 8 registers storing values of one byte each. The first received byte on the axis in port contains command & address: + +* `7 ` reserved +* `6:4` register address +* `3:0` command (`0x0` read, `0x1` write) + +In case of a write command, the payload has to follow with the next byte. In case of a read command, the value of the addressed register is returned on the axis out port. Register at address 0 is special. It contains the version and is read-only. Writes to that register are ignored. ## Further Ressources