From b2e9cf51553667c780427fe36b21b6c1642670a6 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Fri, 30 Dec 2022 21:46:08 +0100 Subject: [PATCH] Remove unneeded synthesis attributes for ring oscillator --- uart_trng/rtl/firo.vhd | 10 +--------- uart_trng/rtl/firo_ctrl.vhd | 4 ++-- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/uart_trng/rtl/firo.vhd b/uart_trng/rtl/firo.vhd index 5ae97b3..81a331b 100644 --- a/uart_trng/rtl/firo.vhd +++ b/uart_trng/rtl/firo.vhd @@ -16,21 +16,13 @@ end entity firo; architecture rtl of firo is - -- signal for inverter loop signal s_ring : std_logic_vector(15 downto 0); signal s_tff : std_logic; - -- attributes for synplify synthesis tool to preserve inverter loop - attribute syn_keep : boolean; - attribute syn_hier : string; - attribute syn_hier of rtl : architecture is "hard"; - attribute syn_keep of s_ring : signal is true; - attribute syn_keep of s_tff : signal is true; - begin firoring : for index in 1 to 15 generate - s_ring(index) <= not(s_ring(index - 1)); + s_ring(index) <= not s_ring(index - 1); end generate; s_ring(0) <= (s_ring(15) xor s_ring(14) xor s_ring(7) xor s_ring(6) xor s_ring(5) xor s_ring(4) xor s_ring(2)) and frun_i; diff --git a/uart_trng/rtl/firo_ctrl.vhd b/uart_trng/rtl/firo_ctrl.vhd index 0c867c7..ce345b8 100644 --- a/uart_trng/rtl/firo_ctrl.vhd +++ b/uart_trng/rtl/firo_ctrl.vhd @@ -41,13 +41,13 @@ architecture rtl of firo_ctrl is signal s_register_din : std_logic_vector(1 downto 0); signal s_register_data : std_logic_vector(8 downto 0); signal s_register_counter : unsigned(2 downto 0); - signal s_register_length : natural range 1 to 2; + signal s_register_length : positive range 1 to 2; signal s_data : std_logic_vector(3 downto 0); begin - frun_o <= s_run when s_register_state = COLLECT else '0'; + frun_o <= s_run when s_register_state = COLLECT else '0'; s_data <= s_neumann_buffer & fdata_i; ControllerP : process (clk_i) is