From d57f683506e59b54a2bd4d0d68f4caae224a79c2 Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Tue, 27 Dec 2022 01:02:47 +0100
Subject: [PATCH] Adapt sim to updated RTL

---
 blink/sim/Makefile     | 11 +++++++----
 blink/sim/tb_blink.vhd | 18 +++++++++++-------
 2 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/blink/sim/Makefile b/blink/sim/Makefile
index cb74226..8abb233 100644
--- a/blink/sim/Makefile
+++ b/blink/sim/Makefile
@@ -1,4 +1,5 @@
 DESIGN_NAME := blink
+LIB_SRC     := ../../lib/components.vhd ../../lib/sim_components.vhd
 RTL_SRC     := ../rtl/${DESIGN_NAME}.vhd
 SIM_SRC     := tb_${DESIGN_NAME}.vhd
 VHD_STD     := 08
@@ -8,11 +9,13 @@ VHD_STD     := 08
 all: sim
 compile: tb_${DESIGN_NAME}
 
-tb_${DESIGN_NAME}: ${RTL_SRC} ${SIM_SRC} | work
+tb_${DESIGN_NAME}: ${LIB_SRC} ${RTL_SRC} ${SIM_SRC} | work
+	@echo "Analyze gatemate library ..."
+	ghdl -a --std=${VHD_STD} -fpsl --workdir=work --work=gatemate ${LIB_SRC}
 	@echo "Analyze testbench & design ..."
-	ghdl -a --std=${VHD_STD} -fpsl --workdir=work ${RTL_SRC} ${SIM_SRC}
+	ghdl -a --std=${VHD_STD} -fpsl --workdir=work -Pwork ${RTL_SRC} ${SIM_SRC}
 	@echo "Elaborate testbench & design ..."
-	ghdl -e --std=${VHD_STD} -fpsl --workdir=work $@
+	ghdl -e --std=${VHD_STD} -fpsl --workdir=work -Pwork $@
 
 sim: tb_${DESIGN_NAME}
 	@echo "Run testbench ..."
@@ -23,4 +26,4 @@ work:
 
 clean:
 	@echo "Cleaning simulation files ..."
-	rm -rf tb_${DESIGN_NAME} *.o *.json work/
+	rm -rf tb_${DESIGN_NAME} *.o work/
diff --git a/blink/sim/tb_blink.vhd b/blink/sim/tb_blink.vhd
index 945047a..c72c982 100644
--- a/blink/sim/tb_blink.vhd
+++ b/blink/sim/tb_blink.vhd
@@ -13,6 +13,7 @@ architecture sim of tb_blink is
 
   signal s_clk   : std_logic := '1';
   signal s_rst_n : std_logic := '0';
+
   signal s_led_n : std_logic_vector(7 downto 0);
 
 begin
@@ -24,21 +25,24 @@ begin
     led_n_o => s_led_n
   );
 
-  s_rst_n <= '1' after 1.2 us;
-  s_clk   <= not s_clk after 500 ns;
+  s_rst_n <= '1' after 120 ns;
+  s_clk   <= not s_clk after 50 ns;
 
-  -- Let's test the first 8 values of LED output
-  process is
+  -- Let's test one complete rotate of LED output
+  TestP : process is
+    variable v_led_n : std_logic_vector(s_led_n'range) := x"FE";
   begin
     wait until s_rst_n;
     wait until rising_edge(s_clk);
     for i in 0 to 7 loop
-      report "LED: " & to_hstring(not s_led_n);
-      assert to_integer(unsigned(not s_led_n)) = i
-        report "LED error, got 0x" & to_hstring(s_led_n) & ", expected 0x" & to_hstring(to_unsigned(255-i, 8))
+      report "LED: " & to_hstring(s_led_n);
+      assert s_led_n = v_led_n
+        report "LED error, got 0x" & to_hstring(s_led_n) & ", expected 0x" & to_hstring(v_led_n)
         severity failure;
       wait until s_led_n'event;
+      v_led_n := v_led_n(6 downto 0) & v_led_n(7);
     end loop;
+    report "Simulation finished :-)";
     stop(0);
   end process;