diff --git a/tlv/risc-v.tlv b/tlv/risc-v.tlv index 35f0c9a..fc1906a 100644 --- a/tlv/risc-v.tlv +++ b/tlv/risc-v.tlv @@ -8,31 +8,7 @@ //--------------------------------------------------------------------------------- - // /====================\ - // | Sum 1 to 9 Program | - // \====================/ - // - // Program to test RV32I - // Add 1,2,3,...,9 (in that order). - // - // Regs: - // x12 (a2): 10 - // x13 (a3): 1..10 - // x14 (a4): Sum - // - m4_asm(ADDI, x14, x0, 0) // Initialize sum register a4 with 0 - m4_asm(ADDI, x12, x0, 1010) // Store count of 10 in register a2. - m4_asm(ADDI, x13, x0, 1) // Initialize loop count register a3 with 0 - // Loop: - m4_asm(ADD, x14, x13, x14) // Incremental summation - m4_asm(ADDI, x13, x13, 1) // Increment loop count by 1 - m4_asm(BLT, x13, x12, 1111111111000) // If a3 is less than a2, branch to label named - m4_asm(ADDI, x0, x0, 1010) // Test for ignored write to reg 0 - // Test result value in x14, and set x30 to reflect pass/fail. - m4_asm(ADDI, x30, x14, 111111010100) // Subtract expected value of 44 to set x30 to 1 if and only iff the result is 45 (1 + 2 + ... + 9). - m4_asm(BGE, x0, x0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0) - m4_asm_end() - m4_define(['M4_MAX_CYC'], 50) + m4_test_prog() //--------------------------------------------------------------------------------- @@ -46,7 +22,8 @@ // Program counter $next_pc[31:0] = $reset ? 32'b0 : - $taken_br ? $br_tgt_br : + $taken_br || $is_jal ? $br_tgt_br : + $is_jalr ? $jalr_tgt_pc : $pc + 4; $pc[31:0] = >>1$next_pc; @@ -90,18 +67,80 @@ $imm_valid = !$is_r_instr; // Instruction code decoding $dec_bits[10:0] = { $funct7[5], $funct3, $opcode }; - $is_beq = $dec_bits ==? 11'bx_000_1100011; - $is_bne = $dec_bits ==? 11'bx_001_1100011; - $is_blt = $dec_bits ==? 11'bx_100_1100011; - $is_bge = $dec_bits ==? 11'bx_101_1100011; - $is_bltu = $dec_bits ==? 11'bx_110_1100011; - $is_bgeu = $dec_bits ==? 11'bx_111_1100011; - $is_addi = $dec_bits ==? 11'bx_000_0010011; - $is_add = $dec_bits == 11'b0_000_0110011; + $is_beq = $dec_bits ==? 11'bx_000_1100011; + $is_bne = $dec_bits ==? 11'bx_001_1100011; + $is_blt = $dec_bits ==? 11'bx_100_1100011; + $is_bge = $dec_bits ==? 11'bx_101_1100011; + $is_bltu = $dec_bits ==? 11'bx_110_1100011; + $is_bgeu = $dec_bits ==? 11'bx_111_1100011; + $is_addi = $dec_bits ==? 11'bx_000_0010011; + $is_add = $dec_bits == 11'b0_000_0110011; + $is_lui = $dec_bits ==? 11'bx_xxx_0110111; + $is_auipc = $dec_bits ==? 11'bx_xxx_0010111; + $is_jal = $dec_bits ==? 11'bx_xxx_1101111; + $is_jalr = $dec_bits ==? 11'bx_000_1100111; + $is_slti = $dec_bits ==? 11'bx_010_0010011; + $is_sltiu = $dec_bits ==? 11'bx_011_0010011; + $is_xori = $dec_bits ==? 11'bx_100_0010011; + $is_ori = $dec_bits ==? 11'bx_110_0010011; + $is_andi = $dec_bits ==? 11'bx_111_0010011; + $is_slli = $dec_bits ==? 11'b0_001_0010011; + $is_srli = $dec_bits ==? 11'b0_101_0010011; + $is_srai = $dec_bits ==? 11'b1_101_0010011; + $is_sub = $dec_bits ==? 11'b1_000_0110011; + $is_sll = $dec_bits ==? 11'b0_001_0110011; + $is_slt = $dec_bits ==? 11'b0_010_0110011; + $is_sltu = $dec_bits ==? 11'b0_011_0110011; + $is_xor = $dec_bits ==? 11'b0_100_0110011; + $is_srl = $dec_bits ==? 11'b0_101_0110011; + $is_sra = $dec_bits ==? 11'b1_101_0110011; + $is_or = $dec_bits ==? 11'b0_110_0110011; + $is_and = $dec_bits ==? 11'b0_111_0110011; + + // LB, LH, LW, LBU, LHU + $is_load = $opcode == 7'b0000011; + // SB, SH, SW + $is_store = $is_s_instr; // ALU - $result[31:0] = $is_addi ? $src1_value + $imm : - $is_add ? $src1_value + $src2_value : + // Some subexpressions + // SLTU & SLTI (set if less than, unsigned) + $sltu_rslt[31:0] = {31'b0, $src1_value < $src2_value}; + $sltiu_rslt[31:0] = {31'b0, $src1_value < $imm}; + // SRA & SRAI (shift right, arithmetic) + // sign-extended src1 + $sext_src1[63:0] = { {32{$src1_value[31]}}, $src1_value }; + // 64-bit sign-extended result + $sra_rslt[63:0] = $sext_src1 >> $src2_value[4:0]; + $srai_rslt[63:0] = $sext_src1 >> $imm[4:0]; + // ALU + $result[31:0] = $is_andi ? $src1_value & $imm : + $is_ori ? $src1_value | $imm : + $is_xori ? $src1_value ^ $imm : + $is_addi | $is_load | $is_store ? $src1_value + $imm : + $is_slli ? $src1_value << $imm[5:0] : + $is_srli ? $src1_value >> $imm[5:0] : + $is_and ? $src1_value & $src2_value : + $is_or ? $src1_value | $src2_value : + $is_xor ? $src1_value ^ $src2_value : + $is_add ? $src1_value + $src2_value : + $is_sub ? $src1_value - $src2_value : + $is_sll ? $src1_value << $src2_value[4:0] : + $is_srl ? $src1_value >> $src2_value[4:0] : + $is_sltu ? $sltu_rslt : + $is_sltiu ? $sltiu_rslt : + $is_lui ? {$imm[31:12], 12'b0} : + $is_auipc ? $pc + $imm : + $is_jal ? $pc + 4 : + $is_jalr ? $pc + 4 : + $is_slt ? (($src1_value[31] == $src2_value[31]) ? + $sltu_rslt : + {31'b0, $src1_value[31]}) : + $is_slti ? (($src1_value[31] == $imm[31]) ? + $sltiu_rslt : + {31'b0, $src1_value[31]}) : + $is_sra ? $sra_rslt[31:0] : + $is_srai ? $srai_rslt[31:0] : 32'b0; // Branch logic @@ -115,17 +154,14 @@ $is_bgeu ? $src1_value >= $src2_value : 1'b0; $br_tgt_br[31:0] = $pc + $imm; + $jalr_tgt_pc[31:0] = $src1_value + $imm; // Assert these to end simulation (before Makerchip cycle limit). - //*passed m4+tb(); *failed = *cyc_cnt > M4_MAX_CYC; - `BOGUS_USE($rd $rd_valid $rs1 $rs1_valid $rs2 $rs2_valid - $funct3 $funct3_valid $funct7 $funct7_valid $imm_valid $imm) - - m4+rf(32, 32, $reset, $rd != 5'b00000 ? $rd_valid : 1'b0, $rd, $result, $rs1_valid, $rs1, $src1_value, $rs2_valid, $rs2, $src2_value) - //m4+dmem(32, 32, $reset, $addr[4:0], $wr_en, $wr_data[31:0], $rd_en, $rd_data) + m4+rf(32, 32, $reset, $rd != 5'b00000 ? $rd_valid : 1'b0, $rd, $is_load ? $ld_data : $result, $rs1_valid, $rs1, $src1_value, $rs2_valid, $rs2, $src2_value) + m4+dmem(32, 32, $reset, $result[6:2], $is_store, $src2_value, $is_load, $ld_data) m4+cpu_viz() \SV - endmodule + endmodule \ No newline at end of file