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285 lines
12 KiB
285 lines
12 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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use work.risc_v_pkg.all;
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entity risc_v is
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port (
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reset_n_i : in std_logic;
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clk_i : in std_logic;
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-- test out
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reg_file_o : out t_reg_file;
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dmem_o : out t_dmem
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);
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end entity;
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architecture rtl of risc_v is
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signal s_reg_file : t_reg_file;
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signal s_dmem : t_dmem;
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signal s_instr : std_logic_vector(31 downto 0);
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signal s_imm : std_logic_vector(31 downto 0);
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signal s_dec_bits : std_logic_vector(10 downto 0);
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signal s_src1_value : std_logic_vector(31 downto 0);
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signal s_src2_value : std_logic_vector(31 downto 0);
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signal s_ld_data : std_logic_vector(31 downto 0);
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signal s_result : std_logic_vector(31 downto 0);
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signal s_sltu_rslt : std_logic_vector(31 downto 0);
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signal s_sltiu_rslt : std_logic_vector(31 downto 0);
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signal s_pc : unsigned(31 downto 0);
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signal s_next_pc : unsigned(31 downto 0);
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signal s_br_tgt_br : unsigned(31 downto 0);
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signal s_jalr_tgt_pc : unsigned(31 downto 0);
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signal s_taken_br : boolean;
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signal s_is_r_instr : boolean;
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signal s_is_i_instr : boolean;
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signal s_is_s_instr : boolean;
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signal s_is_b_instr : boolean;
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signal s_is_u_instr : boolean;
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signal s_is_j_instr : boolean;
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signal s_rd_valid : boolean;
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signal s_funct3_valid : boolean;
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signal s_rs1_valid : boolean;
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signal s_rs2_valid : boolean;
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signal s_funct7_valid : boolean;
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signal s_imm_valid : boolean;
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signal s_is_lui : boolean;
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signal s_is_auipc : boolean;
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signal s_is_jal : boolean;
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signal s_is_jalr : boolean;
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signal s_is_beq : boolean;
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signal s_is_bne : boolean;
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signal s_is_blt : boolean;
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signal s_is_bge : boolean;
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signal s_is_bltu : boolean;
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signal s_is_bgeu : boolean;
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signal s_is_addi : boolean;
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signal s_is_slti : boolean;
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signal s_is_sltiu : boolean;
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signal s_is_xori : boolean;
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signal s_is_ori : boolean;
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signal s_is_andi : boolean;
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signal s_is_slli : boolean;
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signal s_is_srli : boolean;
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signal s_is_srai : boolean;
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signal s_is_add : boolean;
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signal s_is_sub : boolean;
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signal s_is_sll : boolean;
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signal s_is_slt : boolean;
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signal s_is_sltu : boolean;
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signal s_is_xor : boolean;
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signal s_is_srl : boolean;
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signal s_is_sra : boolean;
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signal s_is_or : boolean;
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signal s_is_and : boolean;
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signal s_is_load : boolean;
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signal s_is_store : boolean;
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signal s_src_sgn_eq : boolean;
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signal s_imm_sgn_eq : boolean;
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alias a_opcode : std_logic_vector(6 downto 0) is s_instr(6 downto 0);
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alias a_rd : std_logic_vector(4 downto 0) is s_instr(11 downto 7);
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alias a_funct3 : std_logic_vector(2 downto 0) is s_instr(14 downto 12);
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alias a_rs1 : std_logic_vector(4 downto 0) is s_instr(19 downto 15);
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alias a_rs2 : std_logic_vector(4 downto 0) is s_instr(24 downto 20);
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alias a_funct7 : std_logic_vector(6 downto 0) is s_instr(31 downto 25);
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begin
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-- Test outs
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reg_file_o <= s_reg_file;
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dmem_o <= s_dmem;
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-- prog counter next state logic
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s_next_pc <= 32x"0" when not reset_n_i else
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s_br_tgt_br when s_taken_br or s_is_jal else
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s_jalr_tgt_pc when s_is_jalr else
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s_pc + 4;
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-- prog counter register
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process (clk_i) is
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begin
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if rising_edge(clk_i) then
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s_pc <= s_next_pc;
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end if;
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end process;
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-- Instruction memory
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s_instr <= c_imem(to_integer(s_pc(31 downto 2)));
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-- Decode
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-- Decode instruction type
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s_is_r_instr <= s_instr(6 downto 2) = "01011" or
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s_instr(6 downto 2) = "01100" or
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s_instr(6 downto 2) = "01110" or
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s_instr(6 downto 2) = "10100";
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s_is_i_instr <= std_match(s_instr(6 downto 2), "0000-") or
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std_match(s_instr(6 downto 2), "001-0") or
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s_instr(6 downto 2) = "11001";
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s_is_s_instr <= std_match(s_instr(6 downto 2), "0100-");
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s_is_b_instr <= s_instr(6 downto 2) = "11000";
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s_is_u_instr <= std_match(s_instr(6 downto 2), "0-101");
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s_is_j_instr <= s_instr(6 downto 2) = "11011";
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-- Extract instruction fields
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s_imm <= (31 downto 11 => s_instr(31),
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10 downto 0 => s_instr(30 downto 20)) when s_is_i_instr else
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(31 downto 11 => s_instr(31),
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10 downto 5 => s_instr(30 downto 25),
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4 downto 0 => s_instr(11 downto 7)) when s_is_s_instr else
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(31 downto 12 => s_instr(31),
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11 => s_instr(7),
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10 downto 5 => s_instr(30 downto 25),
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4 downto 1 => s_instr(11 downto 8),
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0 => '0') when s_is_b_instr else
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( 31 => s_instr(31),
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30 downto 12 => s_instr(30 downto 12),
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11 downto 0 => 12x"0") when s_is_u_instr else
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(31 downto 20 => s_instr(31),
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19 downto 12 => s_instr(19 downto 12),
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11 => s_instr(20),
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10 downto 1 => s_instr(30 downto 21),
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0 => '0') when s_is_j_instr else
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32x"0";
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-- Calculate instruction fields valids
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s_rd_valid <= s_is_r_instr or s_is_i_instr or s_is_u_instr or s_is_j_instr;
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s_funct3_valid <= s_is_r_instr or s_is_i_instr or s_is_s_instr or s_is_b_instr;
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s_rs1_valid <= s_funct3_valid;
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s_rs2_valid <= s_is_r_instr or s_is_s_instr or s_is_b_instr;
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s_funct7_valid <= s_is_r_instr;
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s_imm_valid <= not s_is_r_instr;
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-- Instruction code decoding
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s_dec_bits <= (a_funct7(5), a_funct3, a_opcode);
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s_is_lui <= std_match(s_dec_bits, b"-_---_0110111");
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s_is_auipc <= std_match(s_dec_bits, b"-_---_0010111");
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s_is_jal <= std_match(s_dec_bits, b"-_---_1101111");
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s_is_jalr <= std_match(s_dec_bits, b"-_000_1100111");
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s_is_beq <= std_match(s_dec_bits, b"-_000_1100011");
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s_is_bne <= std_match(s_dec_bits, b"-_001_1100011");
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s_is_blt <= std_match(s_dec_bits, b"-_100_1100011");
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s_is_bge <= std_match(s_dec_bits, b"-_101_1100011");
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s_is_bltu <= std_match(s_dec_bits, b"-_110_1100011");
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s_is_bgeu <= std_match(s_dec_bits, b"-_111_1100011");
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s_is_addi <= std_match(s_dec_bits, b"-_000_0010011");
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s_is_slti <= std_match(s_dec_bits, b"-_010_0010011");
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s_is_sltiu <= std_match(s_dec_bits, b"-_011_0010011");
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s_is_xori <= std_match(s_dec_bits, b"-_100_0010011");
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s_is_ori <= std_match(s_dec_bits, b"-_110_0010011");
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s_is_andi <= std_match(s_dec_bits, b"-_111_0010011");
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s_is_slli <= s_dec_bits = b"0_001_0010011";
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s_is_srli <= s_dec_bits = b"0_101_0010011";
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s_is_srai <= s_dec_bits = b"1_101_0010011";
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s_is_add <= s_dec_bits = b"0_000_0110011";
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s_is_sub <= s_dec_bits = b"1_000_0110011";
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s_is_sll <= s_dec_bits = b"0_001_0110011";
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s_is_slt <= s_dec_bits = b"0_010_0110011";
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s_is_sltu <= s_dec_bits = b"0_011_0110011";
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s_is_xor <= s_dec_bits = b"0_100_0110011";
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s_is_srl <= s_dec_bits = b"0_101_0110011";
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s_is_sra <= s_dec_bits = b"1_101_0110011";
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s_is_or <= s_dec_bits = b"0_110_0110011";
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s_is_and <= s_dec_bits = b"0_111_0110011";
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-- LB, LH, LW, LBU, LHU
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s_is_load <= a_opcode = "0000011";
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-- SB, SH, SW
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s_is_store <= s_is_s_instr;
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-- Some subexpressions
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s_src_sgn_eq <= s_src1_value(31) = s_src2_value(31);
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s_imm_sgn_eq <= s_src1_value(31) = s_imm(31);
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-- SLTU & SLTI (set if less than, unsigned)
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s_sltu_rslt <= 31x"0" & to_std_logic(unsigned(s_src1_value) < unsigned(s_src2_value));
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s_sltiu_rslt <= 31x"0" & to_std_logic(unsigned(s_src1_value) < unsigned(s_imm));
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-- ALU
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s_result <=
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s_src1_value and s_imm when s_is_andi else
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s_src1_value or s_imm when s_is_ori else
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s_src1_value xor s_imm when s_is_xori else
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std_logic_vector(signed(s_src1_value) + signed(s_imm)) when s_is_addi or
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s_is_load or
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s_is_store else
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shift_left(s_src1_value, s_imm(5 downto 0)) when s_is_slli else
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shift_right(s_src1_value, s_imm(5 downto 0)) when s_is_srli else
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s_src1_value and s_src2_value when s_is_and else
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s_src1_value or s_src2_value when s_is_or else
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s_src1_value xor s_src2_value when s_is_xor else
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std_logic_vector(signed(s_src1_value) + signed(s_src2_value)) when s_is_add else
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std_logic_vector(signed(s_src1_value) - signed(s_src2_value)) when s_is_sub else
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shift_left(s_src1_value, s_src2_value(4 downto 0)) when s_is_sll else
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shift_right(s_src1_value, s_src2_value(4 downto 0)) when s_is_srl else
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s_sltu_rslt when s_is_sltu else
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s_sltiu_rslt when s_is_sltiu else
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s_imm(31 downto 12) & 12x"0" when s_is_lui else
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std_logic_vector(s_pc + unsigned(s_imm)) when s_is_auipc else
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std_logic_vector(s_pc + 4) when s_is_jal or
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s_is_jalr else
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s_sltu_rslt when s_is_slt and
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s_src_sgn_eq else
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31x"0" & s_src1_value(31) when s_is_slt else
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s_sltiu_rslt when s_is_slti and
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s_imm_sgn_eq else
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31x"0" & s_src1_value(31) when s_is_slti else
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shift_arith_right(s_src1_value, s_src2_value(4 downto 0)) when s_is_sra else
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shift_arith_right(s_src1_value, s_imm(4 downto 0)) when s_is_srai else
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32x"0";
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-- Branch logic
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s_taken_br <= s_src1_value = s_src2_value when s_is_beq else
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s_src1_value /= s_src2_value when s_is_bne else
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signed(s_src1_value) < signed(s_src2_value) when s_is_blt else
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signed(s_src1_value) >= signed(s_src2_value) when s_is_bge else
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unsigned(s_src1_value) < unsigned(s_src2_value) when s_is_bltu else
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unsigned(s_src1_value) >= unsigned(s_src2_value) when s_is_bgeu else
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false;
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s_br_tgt_br <= s_pc + unsigned(s_imm);
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s_jalr_tgt_pc <= unsigned(s_src1_value) + unsigned(s_imm);
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-- Register file
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process (clk_i) is
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variable v_value : std_logic_vector(31 downto 0);
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begin
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if rising_edge(clk_i) then
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if reset_n_i = '0' then
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s_reg_file <= init_reg_file;
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elsif s_rd_valid and a_rd /= 5x"0" then
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v_value := std_logic_vector(s_ld_data) when s_is_load else s_result;
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s_reg_file(to_integer(unsigned(a_rd))) <= v_value;
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end if;
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end if;
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end process;
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s_src1_value <= s_reg_file(to_integer(unsigned(a_rs1))) when s_rs1_valid else
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(others => '0');
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s_src2_value <= s_reg_file(to_integer(unsigned(a_rs2))) when s_rs2_valid else
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(others => '0');
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-- Data memory
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process (clk_i) is
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begin
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if rising_edge(clk_i) then
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if reset_n_i = '0' then
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s_dmem <= init_dmem;
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elsif s_is_store then
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s_dmem(to_integer(unsigned(s_result(6 downto 2)))) <= std_logic_vector(s_src2_value);
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end if;
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end if;
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end process;
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s_ld_data <= s_dmem(to_integer(unsigned(s_result(6 downto 2)))) when s_is_load else
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(others => '0');
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end architecture rtl;
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