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69 lines
1.6 KiB
69 lines
1.6 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.all;
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use work.risc_v_pkg.all;
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entity tb_risc_v is
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end entity tb_risc_v;
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architecture sim of tb_risc_v is
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signal s_clk : std_logic := '1';
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signal s_reset_n : std_logic := '0';
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signal s_reg_file : t_reg_file;
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signal s_dmem : t_dmem;
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begin
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s_clk <= not s_clk after 5 ns;
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s_reset_n <= '1' after 20 ns;
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DUT : entity work.risc_v
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port map (
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reset_n_i => s_reset_n,
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clk_i => s_clk,
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reg_file_o => s_reg_file,
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dmem_o => s_dmem
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);
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-- Checker
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process is
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variable v_expected : std_logic_vector(31 downto 0);
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begin
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wait until s_reset_n = '1';
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-- until program is finished
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wait for c_imem'length * 10 ns;
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-- Check register file entries
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for i in t_reg_file'range loop
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case i is
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when 0 => v_expected := 32x"0";
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when 1 => v_expected := 32x"15";
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when 2 => v_expected := 32x"7";
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when 3 => v_expected := x"FFFFFFFC";
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when 4 => v_expected := 32x"B4";
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when 31 => v_expected := 32x"1F";
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when others => v_expected := 32x"1";
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end case;
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check_equal(s_reg_file(i), v_expected, "Reg. x" & to_string(i) & ": ");
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end loop;
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-- Check data memory entries
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for i in t_dmem'range loop
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case i is
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when 2 => v_expected := 32x"15";
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when others => v_expected := std_logic_vector(to_unsigned(t_dmem'high-i, 32));
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end case;
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check_equal(s_dmem(i), v_expected, "Dmem @" & to_string(i) & ": ");
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end loop;
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stop(0);
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end process;
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end architecture sim;
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