From 308e33cd0c1ac329b3d6783f3fcbfc904e2d2868 Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Tue, 18 Nov 2014 17:08:28 +0100
Subject: [PATCH] synthesis don't like the std_logic'val(int) construct, change
 to if/else instead

---
 syn/SpiSlaveE.vhd | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/syn/SpiSlaveE.vhd b/syn/SpiSlaveE.vhd
index 05ce36f..548e1c0 100644
--- a/syn/SpiSlaveE.vhd
+++ b/syn/SpiSlaveE.vhd
@@ -75,7 +75,11 @@ begin
   SpiSyncP : process (Reset_n_i, Clk_i) is
   begin
     if (Reset_n_i = '0') then
-      s_sclk_d <= (others => std_logic'val(G_SPI_CPOL+2));
+      if (G_SPI_CPOL = '0') then
+        s_sclk_d <= (others => '0');
+      else
+        s_sclk_d <= (others => '1');
+      end if;
       s_ste_d  <= (others => '1');
       s_mosi_d <= (others => '0');
     elsif rising_edge(Clk_i) then