From 389b3470f11e7dc6b4ba4d1c7247247e0d2965f7 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Sat, 15 Nov 2014 23:30:36 +0100 Subject: [PATCH] add cpha parameter do spi_master & spi_slave; change unit test to check all combinations of cpol & cpha --- sim/SimP.vhd | 78 +++++++++++++++++++++++++++++++++------------------ test/SimT.vhd | 52 ++++++++++++++++++++-------------- 2 files changed, 82 insertions(+), 48 deletions(-) diff --git a/sim/SimP.vhd b/sim/SimP.vhd index 29a5ae7..3cf1ab6 100644 --- a/sim/SimP.vhd +++ b/sim/SimP.vhd @@ -1,6 +1,5 @@ library ieee; use ieee.std_logic_1164.all; - --use ieee.numeric_std.all; library libvhdl; use libvhdl.AssertP.all; @@ -12,15 +11,16 @@ package SimP is procedure wait_cycles (signal clk : in std_logic; n : in natural); - procedure spi_master (data_in : in std_logic_vector; data_out : out std_logic_vector; - signal sclk : inout std_logic; signal ste : out std_logic; - signal mosi : out std_logic; signal miso : in std_logic; - cpol : in natural range 0 to 1; period : in time); + procedure spi_master ( data_in : in std_logic_vector; data_out : out std_logic_vector; + signal sclk : inout std_logic; signal ste : out std_logic; + signal mosi : out std_logic; signal miso : in std_logic; + cpol : in natural range 0 to 1; cpha : in natural range 0 to 1; + period : in time); - procedure spi_slave (data_in : in std_logic_vector; data_out : out std_logic_vector; - signal sclk : in std_logic; signal ste : in std_logic; - signal mosi : in std_logic; signal miso : out std_logic; - cpol : in natural range 0 to 1); + procedure spi_slave ( data_in : in std_logic_vector; data_out : out std_logic_vector; + signal sclk : in std_logic; signal ste : in std_logic; + signal mosi : in std_logic; signal miso : out std_logic; + cpol : in natural range 0 to 1; cpha : in natural range 0 to 1); end package SimP; @@ -30,7 +30,7 @@ end package SimP; package body SimP is - -- wait for n rising egdes on clk + -- wait for n rising edges on clk procedure wait_cycles (signal clk : in std_logic; n : in natural) is begin for i in 1 to n loop @@ -39,48 +39,72 @@ package body SimP is end procedure wait_cycles; + -- configurable spi master which supports all combinations of cpol & cpha procedure spi_master ( data_in : in std_logic_vector; data_out : out std_logic_vector; signal sclk : inout std_logic; signal ste : out std_logic; signal mosi : out std_logic; signal miso : in std_logic; - cpol : in natural range 0 to 1; period : in time) is + cpol : in natural range 0 to 1; cpha : in natural range 0 to 1; + period : in time) is begin assert_equal(data_in'length, data_out'length, "data_in & data_out must have same length!"); sclk <= std_logic'val(cpol+2); ste <= '0'; - mosi <= '1'; - wait for period; - for i in data_in'range loop - sclk <= not(sclk); - mosi <= data_in(i); + if (cpha = 0) then + for i in data_in'range loop + mosi <= data_in(i); + wait for period; + sclk <= not(sclk); + data_out(i) := miso; + wait for period; + sclk <= not(sclk); + end loop; wait for period; - sclk <= not(sclk); - data_out(i) := miso; + else + mosi <= '1'; wait for period; - end loop; + for i in data_in'range loop + sclk <= not(sclk); + mosi <= data_in(i); + wait for period; + sclk <= not(sclk); + data_out(i) := miso; + wait for period; + end loop; + end if; ste <= '1'; mosi <= '1'; wait for period; end procedure spi_master; + -- configurable spi slave which supports all combinations of cpol & cpha procedure spi_slave ( data_in : in std_logic_vector; data_out : out std_logic_vector; signal sclk : in std_logic; signal ste : in std_logic; signal mosi : in std_logic; signal miso : out std_logic; - cpol : in natural range 0 to 1) is + cpol : in natural range 0 to 1; cpha : in natural range 0 to 1) is variable v_cpol : std_logic := std_logic'val(cpol+2); begin assert_equal(data_in'length, data_out'length, "data_in & data_out must have same length!"); miso <= 'Z'; wait until ste = '0'; - for i in data_in'range loop - wait until sclk'event and sclk = not(v_cpol); - miso <= data_in(i); - wait until sclk'event and sclk = v_cpol; - data_out(i) := mosi; - end loop; + if (cpha = 0) then + for i in data_in'range loop + miso <= data_in(i); + wait until sclk'event and sclk = not(v_cpol); + data_out(i) := mosi; + wait until sclk'event and sclk = v_cpol; + end loop; + else + for i in data_in'range loop + wait until sclk'event and sclk = not(v_cpol); + miso <= data_in(i); + wait until sclk'event and sclk = v_cpol; + data_out(i) := mosi; + end loop; + end if; wait until ste = '1'; miso <= 'Z'; end procedure spi_slave; -end package body SimP; \ No newline at end of file +end package body SimP; diff --git a/test/SimT.vhd b/test/SimT.vhd index a30580d..3a3525f 100644 --- a/test/SimT.vhd +++ b/test/SimT.vhd @@ -48,38 +48,48 @@ begin end process SimTestP; + -- Unit test of spi master procedure, checks all combinations + -- of cpol & cpha against spi slave procedure SpiMasterP : process is variable v_slave_data : std_logic_vector(7 downto 0); begin - for i in 0 to 255 loop - spi_master (data_in => std_logic_vector(to_unsigned(i, 8)), - data_out => v_slave_data, - sclk => s_sclk, - ste => s_ste, - mosi => s_mosi, - miso => s_miso, - cpol => 1, - period => 1 us - ); - assert_equal(v_slave_data, std_logic_vector(to_unsigned(i, 8))); + for mode in 0 to 3 loop + for i in 0 to 255 loop + spi_master (data_in => std_logic_vector(to_unsigned(i, 8)), + data_out => v_slave_data, + sclk => s_sclk, + ste => s_ste, + mosi => s_mosi, + miso => s_miso, + cpol => mode / 2, + cpha => mode mod 2, + period => 1 us + ); + assert_equal(v_slave_data, std_logic_vector(to_unsigned(i, 8))); + end loop; end loop; wait; end process SpiMasterP; + -- Unit test of spi slave procedure, checks all combinations + -- of cpol & cpha against spi master procedure SpiSlaveP : process is variable v_master_data : std_logic_vector(7 downto 0); begin - for i in 0 to 255 loop - spi_slave (data_in => std_logic_vector(to_unsigned(i, 8)), - data_out => v_master_data, - sclk => s_sclk, - ste => s_ste, - mosi => s_mosi, - miso => s_miso, - cpol => 1 - ); - assert_equal(v_master_data, std_logic_vector(to_unsigned(i, 8))); + for mode in 0 to 3 loop + for i in 0 to 255 loop + spi_slave (data_in => std_logic_vector(to_unsigned(i, 8)), + data_out => v_master_data, + sclk => s_sclk, + ste => s_ste, + mosi => s_mosi, + miso => s_miso, + cpol => mode / 2, + cpha => mode mod 2 + ); + assert_equal(v_master_data, std_logic_vector(to_unsigned(i, 8))); + end loop; end loop; wait; report "INFO: SimP tests finished successfully";