From 4d5b2d2464ebb942c198cd587549cf2936f31196 Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Mon, 4 Sep 2017 22:19:47 +0200
Subject: [PATCH] Update to new QueueP interface

---
 test/SimT.vhd      | 23 +++++++++++------------
 test/WishBoneT.vhd | 13 ++++++++++---
 2 files changed, 21 insertions(+), 15 deletions(-)

diff --git a/test/SimT.vhd b/test/SimT.vhd
index 0e34d9e..f704d0d 100644
--- a/test/SimT.vhd
+++ b/test/SimT.vhd
@@ -2,13 +2,6 @@ library ieee;
   use ieee.std_logic_1164.all;
   use ieee.numeric_std.all;
 
---+ including vhdl 2008 libraries
---+ These lines can be commented out when using
---+ a simulator with built-in VHDL 2008 support
---library ieee_proposed;
---  use ieee_proposed.standard_additions.all;
---  use ieee_proposed.std_logic_1164_additions.all;
---  use ieee_proposed.numeric_std_additions.all;
 
 library osvvm;
   use osvvm.RandomPkg.all;
@@ -16,7 +9,6 @@ library osvvm;
 library libvhdl;
   use libvhdl.AssertP.all;
   use libvhdl.SimP.all;
-  use libvhdl.QueueP.all;
   use libvhdl.UtilsP.all;
 
 
@@ -43,8 +35,15 @@ architecture sim of SimT is
   signal s_mosi : std_logic;
   signal s_miso : std_logic;
 
-  shared variable sv_mosi_queue : t_list_queue;
-  shared variable sv_miso_queue : t_list_queue;
+  package SlvQueue is new libvhdl.QueueP
+    generic map (
+      QUEUE_TYPE => std_logic_vector(C_DATA_WIDTH-1 downto 0),
+      MAX_LEN    => 32,
+      to_string  => to_hstring
+    );
+
+  shared variable sv_mosi_queue : SlvQueue.t_list_queue;
+  shared variable sv_miso_queue : SlvQueue.t_list_queue;
 
 
 begin
@@ -55,8 +54,8 @@ begin
 
   QueueInitP : process is
   begin
-    sv_mosi_queue.init(32);
-    sv_miso_queue.init(32);
+    sv_mosi_queue.init(false);
+    sv_miso_queue.init(false);
     wait;
   end process QueueInitP;
 
diff --git a/test/WishBoneT.vhd b/test/WishBoneT.vhd
index 9992807..0482d5f 100644
--- a/test/WishBoneT.vhd
+++ b/test/WishBoneT.vhd
@@ -9,7 +9,6 @@ library osvvm;
 library libvhdl;
   use libvhdl.AssertP.all;
   use libvhdl.SimP.all;
-  use libvhdl.QueueP.all;
   use libvhdl.UtilsP.all;
 
 library std;
@@ -126,7 +125,15 @@ architecture sim of WishBoneT is
 
   type t_register is array (0 to integer'(2**C_ADDRESS_WIDTH-1)) of std_logic_vector(C_DATA_WIDTH-1 downto 0);
 
-  shared variable sv_wishbone_queue : t_list_queue;
+
+  package SlvQueue is new libvhdl.QueueP
+    generic map (
+      QUEUE_TYPE => std_logic_vector(C_ADDRESS_WIDTH-1 downto 0),
+      MAX_LEN    => 2**C_ADDRESS_WIDTH,
+      to_string  => to_hstring
+    );
+
+  shared variable sv_wishbone_queue : SlvQueue.t_list_queue;
 
   package IntSlvDict is new libvhdl.DictP
     generic map (KEY_TYPE         => integer,
@@ -150,7 +157,7 @@ begin
 
   QueueInitP : process is
   begin
-    sv_wishbone_queue.init(2**C_ADDRESS_WIDTH);
+    sv_wishbone_queue.init(false);
     sv_wishbone_dict.init(false);
     wait;
   end process QueueInitP;