From 5e7db54e8f90bb50eeee97d96d865e8c166febbd Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Tue, 18 Nov 2014 17:01:52 +0100
Subject: [PATCH] add implementation results for SpiSlave component

---
 README.md | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index d497663..a2f74b3 100644
--- a/README.md
+++ b/README.md
@@ -42,7 +42,11 @@ Package with various implementations of queue types:
 Synthesizable components for implementing in FPGA
 
 ##### SpiSlaveE
-Configurable SPI slave with support modes 0-3 and simple VAI local backend
+Configurable SPI slave with support modes 0-3 and simple VAI local backend.
+Implementation results:
+
+* 49 logic elements utilization, 397 MHz clock frequency on Microsemi SmartFusion2, speed grade STD
+* 24 slices utilization, 649 MHz clock frequency on Xilinx Kintex7, speed grade -3
 
 
 ##test