From 8e9b061a7119ce2986b54c0f9cd21070da09587d Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Tue, 21 Jul 2020 02:07:41 +0200
Subject: [PATCH] Use xor_reduce() of UtilsP package

---
 syn/UartRx.vhd | 9 ++++-----
 syn/UartTx.vhd | 9 ++++-----
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/syn/UartRx.vhd b/syn/UartRx.vhd
index 4091b36..5a0185d 100644
--- a/syn/UartRx.vhd
+++ b/syn/UartRx.vhd
@@ -22,6 +22,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+library libvhdl;
+use libvhdl.UtilsP.all;
+
 
 
 entity UartRx is
@@ -47,12 +50,8 @@ architecture rtl of UartRx is
 
 
   function odd_parity (data : in std_logic_vector(DATA_LENGTH-1 downto 0)) return std_logic is
-    variable v_data : std_logic := '0';
   begin
-    for i in data'range loop
-      v_data := v_data xor data(i);
-    end loop;
-    return not v_data;
+    return not xor_reduce(data);
   end function odd_parity;
 
   function to_integer (data : in boolean) return integer is
diff --git a/syn/UartTx.vhd b/syn/UartTx.vhd
index fa58765..28d0be1 100644
--- a/syn/UartTx.vhd
+++ b/syn/UartTx.vhd
@@ -22,6 +22,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
+library libvhdl;
+use libvhdl.UtilsP.all;
+
 
 
 entity UartTx is
@@ -46,12 +49,8 @@ architecture rtl of UartTx is
 
 
   function odd_parity (data : in std_logic_vector(DATA_LENGTH-1 downto 0)) return std_logic is
-    variable v_data : std_logic := '0';
   begin
-    for i in data'range loop
-      v_data := v_data xor data(i);
-    end loop;
-    return not v_data;
+    return not xor_reduce(data);
   end function odd_parity;
 
   function to_integer (data : in boolean) return integer is