From a21373945a826f55f934bbd0b0ce7183461b2ee8 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Fri, 21 Aug 2015 16:19:40 +0200 Subject: [PATCH] New folder common with package UtilP The new common folder holds packages and designs, which can be used either for synthesis & simulation. The first file is UtilP.vhd, a package containing vatious helper functions: * and_reduce(): function to and'ring all items of a vector, overloaded for std_logic_vector & boolean_vector * or_reduce(): function to or'ring all items of a vector, overloaded for std_logic_vector & boolean_vector * even_parity(): calculate the even parity of a std_logic_vector * odd_parity(): calculate the odd parity of a std_logic_vector --- common/UtilsP.vhd | 88 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 common/UtilsP.vhd diff --git a/common/UtilsP.vhd b/common/UtilsP.vhd new file mode 100644 index 0000000..a9f9fac --- /dev/null +++ b/common/UtilsP.vhd @@ -0,0 +1,88 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + + + +package UtilsP is + + + function and_reduce (data : in std_logic_vector) return std_logic; + function and_reduce (data : in boolean_vector) return boolean; + + function or_reduce (data : in std_logic_vector) return std_logic; + function or_reduce (data : in boolean_vector) return boolean; + + function even_parity (data : in std_logic_vector) return std_logic; + function odd_parity (data : in std_logic_vector) return std_logic; + + +end package UtilsP; + + + +package body UtilsP is + + + function and_reduce (data : in std_logic_vector) return std_logic is + begin + for i in data'range loop + if data(i) = '0' then + return '0'; + end if; + end loop; + return '1'; + end function and_reduce; + + function and_reduce (data : in boolean_vector) return boolean is + begin + for i in data'range loop + if (not(data(i))) then + return false; + end if; + end loop; + return true; + end function and_reduce; + + + function or_reduce (data : in std_logic_vector) return std_logic is + begin + for i in data'range loop + if data(i) = '1' then + return '1'; + end if; + end loop; + return '0'; + end function or_reduce; + + function or_reduce (data : in boolean_vector) return boolean is + begin + for i in data'range loop + if data(i) then + return true; + end if; + end loop; + return false; + end function or_reduce; + + + function even_parity (data : in std_logic_vector) return std_logic is + variable v_return : std_logic := '0'; + begin + for i in data'range loop + v_return := v_return xor data(i); + end loop; + return v_return; + end function even_parity; + + function odd_parity (data : in std_logic_vector) return std_logic is + variable v_return : std_logic := '1'; + begin + for i in data'range loop + v_return := v_return xor data(i); + end loop; + return v_return; + end function odd_parity; + + +end package body UtilsP;