From d12f791556cf85a70de1c9601e67fd011d80d88b Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Tue, 18 Nov 2014 18:27:32 +0100
Subject: [PATCH] beautify

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index a2f74b3..ffef499 100644
--- a/README.md
+++ b/README.md
@@ -45,8 +45,8 @@ Synthesizable components for implementing in FPGA
 Configurable SPI slave with support modes 0-3 and simple VAI local backend.
 Implementation results:
 
-* 49 logic elements utilization, 397 MHz clock frequency on Microsemi SmartFusion2, speed grade STD
-* 24 slices utilization, 649 MHz clock frequency on Xilinx Kintex7, speed grade -3
+* Microsemi SmartFusion2 (speed grade std): 49 logic elements, 397 MHz on
+* Xilinx Kintex7 (speed grade -3): 24 slices, 649 MHz on
 
 
 ##test