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110 lines
3.0 KiB
110 lines
3.0 KiB
library ieee;
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use ieee.std_logic_1164.all;
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package WishBoneP is
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component WishBoneMasterE is
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generic (
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Coverage : boolean := false;
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Formal : boolean := false;
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Simulation : boolean := false;
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AddressWidth : natural := 8;
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DataWidth : natural := 8
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);
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone outputs
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WbCyc_o : out std_logic;
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WbStb_o : out std_logic;
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WbWe_o : out std_logic;
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WbAdr_o : out std_logic_vector;
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WbDat_o : out std_logic_vector;
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--+ wishbone inputs
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WbDat_i : in std_logic_vector;
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WbAck_i : in std_logic;
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WbErr_i : in std_logic;
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--+ local register if
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LocalWen_i : in std_logic;
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LocalRen_i : in std_logic;
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LocalAdress_i : in std_logic_vector;
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LocalData_i : in std_logic_vector;
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LocalData_o : out std_logic_vector;
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LocalAck_o : out std_logic;
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LocalError_o : out std_logic
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);
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end component WishBoneMasterE;
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component WishBoneSlaveE is
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generic (
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Formal : boolean := false;
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Simulation : boolean := false;
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AddressWidth : natural := 32;
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DataWidth : natural := 32
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);
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone inputs
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WbCyc_i : in std_logic;
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WbStb_i : in std_logic;
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WbWe_i : in std_logic;
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WbAdr_i : in std_logic_vector;
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WbDat_i : in std_logic_vector;
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--* wishbone outputs
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WbDat_o : out std_logic_vector;
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WbAck_o : out std_logic;
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WbErr_o : out std_logic;
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--+ local register if
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LocalWen_o : out std_logic;
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LocalRen_o : out std_logic;
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LocalAdress_o : out std_logic_vector;
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LocalData_o : out std_logic_vector;
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LocalData_i : in std_logic_vector
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);
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end component WishBoneSlaveE;
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component WishBoneCheckerE is
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port (
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--+ wishbone system if
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WbRst_i : in std_logic;
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WbClk_i : in std_logic;
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--+ wishbone outputs
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WbMCyc_i : in std_logic;
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WbMStb_i : in std_logic;
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WbMWe_i : in std_logic;
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WbMAdr_i : in std_logic_vector;
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WbMDat_i : in std_logic_vector;
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--+ wishbone inputs
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WbSDat_i : in std_logic_vector;
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WbSAck_i : in std_logic;
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WbSErr_i : in std_logic;
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WbRty_i : in std_logic
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);
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end component WishBoneCheckerE;
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type t_wishbone_if is record
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--+ wishbone outputs
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Cyc : std_logic;
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Stb : std_logic;
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We : std_logic;
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Adr : std_logic_vector;
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WDat : std_logic_vector;
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--+ wishbone inputs
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RDat : std_logic_vector;
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Ack : std_logic;
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Err : std_logic;
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end record t_wishbone_if;
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end package WishBoneP;
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