diff --git a/README.md b/README.md
index 69e714e..2e3f320 100644
--- a/README.md
+++ b/README.md
@@ -23,9 +23,12 @@ The next two lists will grow during further development
 * cover directive
 * assume directive (synthesis)
 * restrict directive (synthesis)
+
 * always operator
+* before operator (GHDL crash with a specific property, see psl_before.vhd)
+* eventually! operator (simulation, synthesis produces a GHDL crash, see psl_eventually.vhd)
+* logical implication operator
 * never operator
-* implication operator
 * next operator
 * next[n] operator
 * next_a[i to j] operator
@@ -35,13 +38,11 @@ The next two lists will grow during further development
 * next_event_e[i to j] operator
 * until operator
 * until_ operator
-* before operator (GHDL crash with a specific property, see psl_before.vhd)
-* eventually! operator (simulation, synthesis produces a GHDL crash, see psl_eventually.vhd)
 
 ## PSL features not yet supported by GHDL:
 
-* Synthesis of strong operator versions
 * forall statement
+* Synthesis of strong operator versions
 
 ## PSL features supported by GHDL but with wrong behaviour
 
diff --git a/formal/psl_logical_implication.sby b/formal/psl_logical_implication.sby
new file mode 100644
index 0000000..2d06026
--- /dev/null
+++ b/formal/psl_logical_implication.sby
@@ -0,0 +1,18 @@
+[tasks]
+prove
+
+[options]
+depth 25
+prove: mode bmc
+
+[engines]
+prove: smtbmc z3
+
+[script]
+prove: ghdl --std=08 pkg.vhd sequencer.vhd psl_logical_implication.vhd -e psl_logical_implication
+prep -top psl_logical_implication
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_logical_implication.vhd
diff --git a/formal/tests.mk b/formal/tests.mk
index 55b44ec..9f4006e 100644
--- a/formal/tests.mk
+++ b/formal/tests.mk
@@ -1,5 +1,6 @@
 psl_tests := \
 psl_always \
+psl_logical_implication \
 psl_never \
 psl_next \
 psl_next_3 \
diff --git a/src/psl_logical_implication.vhd b/src/psl_logical_implication.vhd
new file mode 100644
index 0000000..74ae838
--- /dev/null
+++ b/src/psl_logical_implication.vhd
@@ -0,0 +1,48 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_logical_implication is
+  port (
+    clk : in std_logic
+  );
+end entity psl_logical_implication;
+
+
+architecture psl of psl_logical_implication is
+
+  signal a, b, c, d : std_logic;
+
+begin
+
+
+  --                              012345
+  SEQ_A : sequencer generic map ("_-__-___-__") port map (clk, a);
+  SEQ_B : sequencer generic map ("_-______-__") port map (clk, b);
+  SEQ_C : sequencer generic map ("_-__-______") port map (clk, c);
+  SEQ_D : sequencer generic map ("___________") port map (clk, d);
+
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  IMPLICATION_0_a : assert always (a -> b or c);
+
+  -- This assertion doesn't hold at cycle 4
+  IMPLICATION_1_a : assert always (a -> b and c);
+
+  -- This assertion holds because RHS of implication always holds
+  IMPLICATION_2_a : assert always (a -> true);
+
+  -- This assertion doesn't hold at cycle 1 because RHS of implication never holds
+  IMPLICATION_3_a : assert always (a -> false);
+
+  -- This assertion holds because LHS of implication never holds
+  IMPLICATION_4_a : assert always (d -> (a and b and c));
+
+
+end architecture psl;