From 1acd5e3d6c16d850813bd5c780192ef8529cb862 Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Mon, 11 Jan 2021 12:01:16 +0100
Subject: [PATCH] Add issue code for ghdl/ghdl#1591

---
 issues/issue_1591.vhd | 70 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)
 create mode 100644 issues/issue_1591.vhd

diff --git a/issues/issue_1591.vhd b/issues/issue_1591.vhd
new file mode 100644
index 0000000..242c1ee
--- /dev/null
+++ b/issues/issue_1591.vhd
@@ -0,0 +1,70 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+entity issue is
+  port (
+    clk : in std_logic
+  );
+end entity issue;
+
+
+architecture psl of issue is
+
+  signal a : boolean := true;
+
+begin
+
+
+  testG : if true generate
+
+    signal b : boolean := true;
+    signal c : boolean := false;
+
+  begin
+
+    c <= true;
+
+    -- All is sensitive to rising edge of clk
+    default clock is rising_edge(clk);
+
+    -- This assertion works
+    INITIAL_0_a : assert always a;
+
+    -- This assertion generates an ghdl-yosys-plugin error
+    -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
+    INITIAL_1_a : assert always b;
+
+    -- This assertion works
+    INITIAL_2_a : assert always c;
+
+  end generate testG;
+
+  -- Same error occurs when using a block instead of a generate
+  -- statement
+  testB : block is
+
+    signal b : boolean := true;
+    signal c : boolean := false;
+
+  begin
+
+    c <= true;
+
+    -- All is sensitive to rising edge of clk
+    default clock is rising_edge(clk);
+
+    -- This assertion works
+    INITIAL_0_a : assert always a;
+
+    -- This assertion generates an ghdl-yosys-plugin error
+    -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
+    INITIAL_1_a : assert always b;
+
+    -- This assertion works
+    INITIAL_2_a : assert always c;
+
+  end block testB;
+
+
+end architecture psl;