From 263dcae830ade237f5dfcadd39e03b7cfbd6d8fe Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Sat, 2 May 2020 16:24:59 +0200
Subject: [PATCH] Add sequencer and first examples

* sequencer for easy waveform generation of
  simple 1 bit std_logic signals
* Package with sequencer component delaration
* Examples for always & never operator
---
 src/pkg.vhd        | 19 +++++++++++++++++++
 src/psl_always.vhd | 34 ++++++++++++++++++++++++++++++++++
 src/psl_never.vhd  | 34 ++++++++++++++++++++++++++++++++++
 src/sequencer.vhd  | 40 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 127 insertions(+)
 create mode 100644 src/pkg.vhd
 create mode 100644 src/psl_always.vhd
 create mode 100644 src/psl_never.vhd
 create mode 100644 src/sequencer.vhd

diff --git a/src/pkg.vhd b/src/pkg.vhd
new file mode 100644
index 0000000..6ec3b1e
--- /dev/null
+++ b/src/pkg.vhd
@@ -0,0 +1,19 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+package pkg is
+
+
+  component sequencer is
+    generic (
+      seq : string
+    );
+    port (
+      clk  : in  std_logic;
+      data : out std_logic
+    );
+  end component sequencer;
+
+
+end package pkg;
diff --git a/src/psl_always.vhd b/src/psl_always.vhd
new file mode 100644
index 0000000..1d0dff4
--- /dev/null
+++ b/src/psl_always.vhd
@@ -0,0 +1,34 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_always is
+  port (
+    clk : in std_logic
+  );
+end entity psl_always;
+
+
+architecture psl of psl_always is
+
+  signal a : std_logic;
+
+begin
+
+
+  SEQ : sequencer generic map ("_-_-_") port map (clk, a);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- Signal a has to be low at cycle 0 only
+  WITHOUT_ALWAYS_a : assert a;
+
+  -- Signal a has to be low forever
+  WITH_ALWAYS_a : assert always a;
+
+
+end architecture psl;
diff --git a/src/psl_never.vhd b/src/psl_never.vhd
new file mode 100644
index 0000000..1e0af4c
--- /dev/null
+++ b/src/psl_never.vhd
@@ -0,0 +1,34 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_never is
+  port (
+    clk : in std_logic
+  );
+end entity psl_never;
+
+
+architecture psl of psl_never is
+
+  signal a : std_logic;
+
+begin
+
+
+  SEQ : sequencer generic map ("_-_-_") port map (clk, a);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- Signal a has to be low forever
+  NEVER_a : assert never a;
+
+  -- Equivalent assert with always and negation
+  ALWAYS_a : assert always not a;
+
+
+end architecture psl;
diff --git a/src/sequencer.vhd b/src/sequencer.vhd
new file mode 100644
index 0000000..6b7070c
--- /dev/null
+++ b/src/sequencer.vhd
@@ -0,0 +1,40 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+entity sequencer is
+  generic (
+    seq : string
+  );
+  port (
+    clk  : in  std_logic;
+    data : out std_logic
+  );
+end entity sequencer;
+
+
+architecture rtl of sequencer is
+
+  signal cycle : natural := 0;
+  signal ch    : character;
+
+begin
+
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if (cycle < seq'length) then
+        cycle <= cycle + 1;
+      end if;
+    end if;
+  end process;
+
+  ch <= seq(cycle+1);
+
+  data <= '0' when ch = '0' or ch = '_' else
+          '1' when ch = '1' or ch = '-' else
+          'X';
+
+
+end architecture rtl;
\ No newline at end of file