diff --git a/README.md b/README.md
index a6e21f7..db290fc 100644
--- a/README.md
+++ b/README.md
@@ -70,6 +70,7 @@ The next lists will grow during further development
 
 * Partial support of PSL vunits (synthesis only)
 * Partial support of named sequences (simulation only)
+* Partial support of named properties (simulation only)
 
 ## Not yet supported by GHDL:
 
diff --git a/formal/psl_property.sby b/formal/psl_property.sby
new file mode 100644
index 0000000..1081e3e
--- /dev/null
+++ b/formal/psl_property.sby
@@ -0,0 +1,18 @@
+[tasks]
+bmc
+
+[options]
+depth 25
+bmc: mode bmc
+
+[engines]
+bmc: smtbmc z3
+
+[script]
+bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_property.vhd -e psl_property
+prep -top psl_property
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_property.vhd
diff --git a/sim/tests.mk b/sim/tests.mk
index 6777760..291c54d 100644
--- a/sim/tests.mk
+++ b/sim/tests.mk
@@ -26,4 +26,5 @@ psl_sere_len_matching_and \
 psl_sere_non_len_matching_and \
 psl_sere_concat \
 psl_sere_fusion \
-psl_sequence
+psl_sequence \
+psl_property
diff --git a/src/psl_property.vhd b/src/psl_property.vhd
new file mode 100644
index 0000000..dfa1aa5
--- /dev/null
+++ b/src/psl_property.vhd
@@ -0,0 +1,64 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_property is
+  port (
+    clk : in std_logic
+  );
+end entity psl_property;
+
+
+architecture psl of psl_property is
+
+  signal req, avalid, busy, adone, data, ddone : std_logic;
+
+begin
+
+
+  --                                   01234567890123
+  SEQ_REQ    : sequencer generic map ("_-____________") port map (clk, req);
+  SEQ_AVALID : sequencer generic map ("__-___________") port map (clk, avalid);
+  SEQ_BUSY   : sequencer generic map ("___-_--_______") port map (clk, busy);
+  SEQ_ADONE  : sequencer generic map ("_______-______") port map (clk, adone);
+  SEQ_DATA   : sequencer generic map ("________---___") port map (clk, data);
+  SEQ_DDONE  : sequencer generic map ("___________-__") port map (clk, ddone);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- Transfer property
+  -- Don't works in synthesis, only in simulation
+  property transfer_3 is always (
+    {req} |=> {{avalid; busy[->3]; adone}; {data[->3]; ddone}}
+  );
+
+  -- SERE concatenation operator
+  -- RHS starts at one cycle cycle that the LHS ends
+  -- This assertion holds
+  PROP_0_a : assert transfer_3;
+
+  -- Properties can have parameters
+  -- Don't works in synthesis, only in simulation
+  -- Parameters with repetition operators lead to crash:
+  -- raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : no field Hash
+  property transfer_3_p (boolean v, ad, dd) is always (
+    {req} |=> {{v; busy[->3]; ad}; {data[->3]; dd}}
+  );
+
+  -- SERE concatenation operator
+  -- RHS starts at one cycle cycle that the LHS ends
+  -- This assertion holds
+  PROP_1_a : assert transfer_3_p(avalid, adone, ddone);
+
+  -- Stop simulation after longest running sequencer is finished
+  -- Simulation only code by using pragmas
+  -- synthesis translate_off
+  stop_sim(clk, 13);
+  -- synthesis translate_on
+
+
+end architecture psl;