diff --git a/README.md b/README.md
index 92859b8..bab90a4 100644
--- a/README.md
+++ b/README.md
@@ -46,6 +46,7 @@ The next lists will grow during further development
 ### Sequential Extended Regular Expressions (SERE style)
 
 * Simple SERE
+* Overlapping suffix implication operator
 
 ## PSL features not yet supported by GHDL:
 
diff --git a/formal/psl_sere_overlapping_suffix_impl.sby b/formal/psl_sere_overlapping_suffix_impl.sby
new file mode 100644
index 0000000..b3c2e4c
--- /dev/null
+++ b/formal/psl_sere_overlapping_suffix_impl.sby
@@ -0,0 +1,18 @@
+[tasks]
+prove
+
+[options]
+depth 25
+prove: mode bmc
+
+[engines]
+prove: smtbmc z3
+
+[script]
+prove: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere_overlapping_suffix_impl.vhd -e psl_sere_overlapping_suffix_impl
+prep -top psl_sere_overlapping_suffix_impl
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_sere_overlapping_suffix_impl.vhd
diff --git a/formal/tests.mk b/formal/tests.mk
index 5153683..d012148 100644
--- a/formal/tests.mk
+++ b/formal/tests.mk
@@ -13,4 +13,5 @@ psl_next_event_a \
 psl_until \
 psl_before \
 psl_eventually \
-psl_sere
+psl_sere \
+psl_sere_overlapping_suffix_impl
diff --git a/src/psl_sere_overlapping_suffix_impl.vhd b/src/psl_sere_overlapping_suffix_impl.vhd
new file mode 100644
index 0000000..8544d27
--- /dev/null
+++ b/src/psl_sere_overlapping_suffix_impl.vhd
@@ -0,0 +1,39 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_sere_overlapping_suffix_impl is
+  port (
+    clk : in std_logic
+  );
+end entity psl_sere_overlapping_suffix_impl;
+
+
+architecture psl of psl_sere_overlapping_suffix_impl is
+
+  signal a, b : std_logic;
+
+begin
+
+
+  --                              012345
+  SEQ_A : sequencer generic map ("--___-___") port map (clk, a);
+  SEQ_B : sequencer generic map ("_-____-__") port map (clk, b);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  SERE_0_a : assert always {a; a} |-> {a and b};
+
+  -- This assertion doesn't hold at cycle 2
+  SERE_1_a : assert always {a; a} |-> next {a and b};
+
+  -- This assertion holds
+  SERE_2_a : assert always {not a; a} |-> next {b};
+
+
+end architecture psl;