From 4815ad4a01a9252cdbdd0f99a1c67335c390611b Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Thu, 28 May 2020 10:04:20 +0200
Subject: [PATCH] Add issue code for eventually! operator (ghdl/ghdl#1345)

---
 issues/issue_1345.vhd | 93 +++++++++++++++++++++++++++++++++++++++++++
 issues/tests.mk       |  3 +-
 2 files changed, 95 insertions(+), 1 deletion(-)
 create mode 100644 issues/issue_1345.vhd

diff --git a/issues/issue_1345.vhd b/issues/issue_1345.vhd
new file mode 100644
index 0000000..dba1786
--- /dev/null
+++ b/issues/issue_1345.vhd
@@ -0,0 +1,93 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+entity sequencer is
+  generic (
+    seq : string
+  );
+  port (
+    clk  : in  std_logic;
+    data : out std_logic
+  );
+end entity sequencer;
+
+
+architecture rtl of sequencer is
+
+  signal index : natural := seq'low;
+
+  function to_bit (a : in character) return std_logic is
+    variable ret : std_logic;
+  begin
+    case a is
+      when '0' | '_' => ret := '0';
+      when '1' | '-' => ret := '1';
+      when others    => ret := 'X';
+    end case;
+    return ret;
+  end function to_bit;
+
+begin
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if (index < seq'high) then
+        index <= index + 1;
+      end if;
+    end if;
+  end process;
+
+  data <= to_bit(seq(index));
+
+end architecture rtl;
+
+
+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+
+
+entity issue is
+  port (
+    clk : in std_logic
+  );
+end entity issue;
+
+
+architecture psl of issue is
+
+  component sequencer is
+    generic (
+      seq : string
+    );
+    port (
+      clk  : in  std_logic;
+      data : out std_logic
+    );
+  end component sequencer;
+
+  signal a, b : std_logic;
+
+begin
+
+
+  --                              0123456789012345
+  SEQ_A : sequencer generic map ("__-__-____-_____") port map (clk, a);
+  SEQ_B : sequencer generic map ("_______-______-_") port map (clk, b);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  -- This assertion leads to a GHDL synthesis crash with bug report
+  EVENTUALLY_a : assert always (a -> eventually! b);
+
+
+end architecture psl;
diff --git a/issues/tests.mk b/issues/tests.mk
index cc02a6c..7be1b71 100644
--- a/issues/tests.mk
+++ b/issues/tests.mk
@@ -3,4 +3,5 @@ issue_1288 \
 issue_1292 \
 issue_1314 \
 issue_1321 \
-issue_1322
\ No newline at end of file
+issue_1322 \
+issue_1345