diff --git a/README.md b/README.md
index 2070a49..9b9dcf5 100644
--- a/README.md
+++ b/README.md
@@ -46,6 +46,7 @@ The next lists will grow during further development
 ### Sequential Extended Regular Expressions (SERE style)
 
 * Simple SERE
+* Concatenation operator (`;`)
 * Fusion operator (`:`)
 * Overlapping suffix implication operator (`|->`)
 * Non overlapping suffix implication operator (`|=>`)
diff --git a/formal/psl_sere_concat.sby b/formal/psl_sere_concat.sby
new file mode 100644
index 0000000..cc0ccb6
--- /dev/null
+++ b/formal/psl_sere_concat.sby
@@ -0,0 +1,18 @@
+[tasks]
+bmc
+
+[options]
+depth 25
+bmc: mode bmc
+
+[engines]
+bmc: smtbmc z3
+
+[script]
+bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere_concat.vhd -e psl_sere_concat
+prep -top psl_sere_concat
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_sere_concat.vhd
diff --git a/formal/tests.mk b/formal/tests.mk
index 95b9776..e6a363a 100644
--- a/formal/tests.mk
+++ b/formal/tests.mk
@@ -24,5 +24,6 @@ psl_sere_within \
 psl_sere_or \
 psl_sere_len_matching_and \
 psl_sere_non_len_matching_and \
+psl_sere_concat \
 psl_sere_fusion \
 psl_prev
diff --git a/sim/tests.mk b/sim/tests.mk
index a16f4a1..50c2aa6 100644
--- a/sim/tests.mk
+++ b/sim/tests.mk
@@ -24,4 +24,5 @@ psl_sere_within \
 psl_sere_or \
 psl_sere_len_matching_and \
 psl_sere_non_len_matching_and \
+psl_sere_concat \
 psl_sere_fusion
diff --git a/src/psl_sere_concat.vhd b/src/psl_sere_concat.vhd
new file mode 100644
index 0000000..d9a9a9c
--- /dev/null
+++ b/src/psl_sere_concat.vhd
@@ -0,0 +1,55 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_sere_concat is
+  port (
+    clk : in std_logic
+  );
+end entity psl_sere_concat;
+
+
+architecture psl of psl_sere_concat is
+
+  signal req, avalid, busy, adone, data, ddone : std_logic;
+
+begin
+
+
+  --                                   01234567890123
+  SEQ_REQ    : sequencer generic map ("_-____________") port map (clk, req);
+  SEQ_AVALID : sequencer generic map ("__-___________") port map (clk, avalid);
+  SEQ_BUSY   : sequencer generic map ("___-_--_______") port map (clk, busy);
+  SEQ_ADONE  : sequencer generic map ("_______-______") port map (clk, adone);
+  SEQ_DATA   : sequencer generic map ("________---___") port map (clk, data);
+  SEQ_DDONE  : sequencer generic map ("___________-__") port map (clk, ddone);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- SERE concatenation operator
+  -- RHS starts at one cycle cycle that the LHS ends
+  -- This assertion holds
+  SERE_0_a : assert always {req} |=> {{avalid; busy[->3]; adone}; {data[->3]; ddone}};
+
+  -- SERE concatenation operator
+  -- RHS starts at one cycle cycle that the LHS ends
+  -- This cover holds at cycle 7
+  SERE_0_c : cover {req; avalid; busy[->3]; adone} report "Address phase completed";
+
+  -- SERE concatenation operator
+  -- RHS starts at one cycle cycle that the LHS ends
+  -- This cover holds at cycle 11
+  SERE_1_c : cover {data[->3]; ddone} report "Data phase completed";
+
+  -- Stop simulation after longest running sequencer is finished
+  -- Simulation only code by using pragmas
+  -- synthesis translate_off
+  stop_sim(clk, 13);
+  -- synthesis translate_on
+
+
+end architecture psl;