diff --git a/README.md b/README.md index b016905..e35a7f9 100644 --- a/README.md +++ b/README.md @@ -49,15 +49,16 @@ The next lists will grow during further development * Overlapping suffix implication operator (|->) * Non overlapping suffix implication operator (|=>) * Consecutive repetition operator ([*], [+], [*n], [*i to j]) +* Non consecutive repetition operator ([=n], [=i to j]) +* within operator ## PSL features not yet supported by GHDL: * forall statement * Synthesis of strong operator versions -* SERE non consecutive repetition operator ([=n], [=i to j]) * SERE goto repetition operator ([->], [->n], [->i to j]) -## PSL features supported by GHDL but with wrong behaviour +## PSL features supported by GHDL, behaviour under investigation * before_ operator (Seems that LHS & RHS of operator have to be active at same cycle, see psl_before.vhd) * next_event_a[i to j] operator (Behaviour currently under investigation) diff --git a/formal/psl_sere_consecutive_repeat_repetition.sby b/formal/psl_sere_consecutive_repeat_repetition.sby new file mode 100644 index 0000000..0034c18 --- /dev/null +++ b/formal/psl_sere_consecutive_repeat_repetition.sby @@ -0,0 +1,18 @@ +[tasks] +bmc + +[options] +depth 25 +bmc: mode bmc + +[engines] +bmc: smtbmc z3 + +[script] +bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere_consecutive_repeat_repetition.vhd -e psl_sere_consecutive_repeat_repetition +prep -top psl_sere_consecutive_repeat_repetition + +[files] +../src/pkg.vhd +../src/sequencer.vhd +../src/psl_sere_consecutive_repeat_repetition.vhd diff --git a/formal/tests.mk b/formal/tests.mk index b197819..c68d8db 100644 --- a/formal/tests.mk +++ b/formal/tests.mk @@ -16,4 +16,5 @@ psl_eventually \ psl_sere \ psl_sere_overlapping_suffix_impl \ psl_sere_non_overlapping_suffix_impl \ -psl_sere_consecutive_repetition +psl_sere_consecutive_repetition \ +psl_sere_consecutive_repeat_repetition diff --git a/src/psl_sere_consecutive_repeat_repetition.vhd b/src/psl_sere_consecutive_repeat_repetition.vhd new file mode 100644 index 0000000..87a5593 --- /dev/null +++ b/src/psl_sere_consecutive_repeat_repetition.vhd @@ -0,0 +1,61 @@ +library ieee; + use ieee.std_logic_1164.all; + +use work.pkg.all; + + +entity psl_sere_consecutive_repeat_repetition is + port ( + clk : in std_logic + ); +end entity psl_sere_consecutive_repeat_repetition; + + +architecture psl of psl_sere_consecutive_repeat_repetition is + + signal req, busy, done : std_logic; + +begin + + + -- 0123456789 + SEQ_REQ : sequencer generic map ("_-________") port map (clk, req); + SEQ_BUSY : sequencer generic map ("__-_-_-___") port map (clk, busy); + SEQ_DONE : sequencer generic map ("________-_") port map (clk, done); + + + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + -- Non consecutive repetition of 3 cycles with possible padding + -- busy has to hold on 3 cycles between req & done + -- This assertion holds + SERE_0_a : assert always {req} |=> {busy[=3]; done}; + + -- Non consecutive repetition of 2 to 4 cycles with possible padding + -- busy has to hold on 2 to 4 cycles between req & done + -- This assertion holds + SERE_1_a : assert always {req} |=> {busy[=2 to 4]; done}; + + -- Non consecutive repetition of 5 cycles with possible padding + -- busy has to hold on 5 cycles between req & done + -- This assertion holds -> possible PITFALL! + -- RHS is underspecified, nothing prevents done to hold between or together + -- with holding busy. For intentioned behaviour, the behaviour of done + -- has to be described more specificly (see SERE_3_a) + SERE_2_a : assert always {req} |=> {busy[=5]; done}; + + -- Non consecutive repetition of 3 cycles with possible padding + -- busy has to hold on 3 cycles between req & and the first done + -- This is a more exact version of the assertions before using the + -- within SERE operator (busy[*3] has to hold during done don't holds) + -- This assertion holds + SERE_3_a : assert always {req} |=> {{{busy[=3]} within {not done[+]}}; done}; + + -- Non consecutive repetition of 4 cycles with possible padding + -- busy has to hold on 4 cycles between req & and the first done + -- This assertion doesn't hold at cycle 8 + SERE_4_a : assert always {req} |=> {{{busy[=4]} within {not done[+]}}; done}; + + +end architecture psl;