From 9b342890458ae2a3ad19286d3ba7de7a759b616d Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Sun, 24 May 2020 10:59:45 +0200
Subject: [PATCH] Add example for SERE length mathcing and (&&) operator

---
 formal/psl_sere_len_matching_and.sby | 18 +++++++++++++
 formal/tests.mk                      |  3 ++-
 src/psl_sere_len_matching_and.vhd    | 38 ++++++++++++++++++++++++++++
 src/psl_sere_or.vhd                  |  2 +-
 4 files changed, 59 insertions(+), 2 deletions(-)
 create mode 100644 formal/psl_sere_len_matching_and.sby
 create mode 100644 src/psl_sere_len_matching_and.vhd

diff --git a/formal/psl_sere_len_matching_and.sby b/formal/psl_sere_len_matching_and.sby
new file mode 100644
index 0000000..546bb63
--- /dev/null
+++ b/formal/psl_sere_len_matching_and.sby
@@ -0,0 +1,18 @@
+[tasks]
+bmc
+
+[options]
+depth 25
+bmc: mode bmc
+
+[engines]
+bmc: smtbmc z3
+
+[script]
+bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere_len_matching_and.vhd -e psl_sere_len_matching_and
+prep -top psl_sere_len_matching_and
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_sere_len_matching_and.vhd
diff --git a/formal/tests.mk b/formal/tests.mk
index 3dddc1c..7fab8b7 100644
--- a/formal/tests.mk
+++ b/formal/tests.mk
@@ -21,4 +21,5 @@ psl_sere_non_consecutive_repeat_repetition \
 psl_sere_non_consecutive_goto_repetition \
 psl_cover \
 psl_sere_within \
-psl_sere_or
\ No newline at end of file
+psl_sere_or \
+psl_sere_len_matching_and
\ No newline at end of file
diff --git a/src/psl_sere_len_matching_and.vhd b/src/psl_sere_len_matching_and.vhd
new file mode 100644
index 0000000..7a6a9bc
--- /dev/null
+++ b/src/psl_sere_len_matching_and.vhd
@@ -0,0 +1,38 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_sere_len_matching_and is
+  port (
+    clk : in std_logic
+  );
+end entity psl_sere_len_matching_and;
+
+
+architecture psl of psl_sere_len_matching_and is
+
+  signal req, busy, valid, done : std_logic;
+
+begin
+
+
+  --                                  0123456789
+  SEQ_REQ   : sequencer generic map ("_-________") port map (clk, req);
+  SEQ_BUSY  : sequencer generic map ("__------__") port map (clk, busy);
+  SEQ_VALID : sequencer generic map ("___-_-_-__") port map (clk, valid);
+  SEQ_DONE  : sequencer generic map ("________-_") port map (clk, done);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- Length matching AND two SERE
+  -- valid has to hold 3 times between req & done.
+  -- busy has to hold each cycle between req & done.
+  -- This assertion holds
+  SERE_0_a : assert always {req} |=> {{valid[->3]} && {(busy and not done)[+]}; not busy and done};
+
+
+end architecture psl;
diff --git a/src/psl_sere_or.vhd b/src/psl_sere_or.vhd
index 0dea4df..a73cef7 100644
--- a/src/psl_sere_or.vhd
+++ b/src/psl_sere_or.vhd
@@ -14,7 +14,7 @@ end entity psl_sere_or;
 architecture psl of psl_sere_or is
 
   signal req2, req4, busy, valid, done : std_logic;
-  signal req, wen, ren, ends           : std_logic;
+  signal req, wen, ends                : std_logic;
 
 begin