From 9dc78f37c90c8711d721f3f33c06b4822033061d Mon Sep 17 00:00:00 2001 From: tmeissner Date: Sat, 16 May 2020 12:45:38 +0200 Subject: [PATCH] Simplify sequencer by removing intermediate character signal --- src/hex_sequencer.vhd | 11 ++++------- src/sequencer.vhd | 5 +---- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/hex_sequencer.vhd b/src/hex_sequencer.vhd index ccdda21..9c0b7c1 100644 --- a/src/hex_sequencer.vhd +++ b/src/hex_sequencer.vhd @@ -21,8 +21,7 @@ end entity hex_sequencer; architecture rtl of hex_sequencer is - signal cycle : natural := 0; - signal ch : character; + signal index : natural := seq'low; begin @@ -30,15 +29,13 @@ begin process (clk) is begin if rising_edge(clk) then - if (cycle < seq'length) then - cycle <= cycle + 1; + if (index < seq'high) then + index <= index + 1; end if; end if; end process; - ch <= seq(cycle+1); - - data <= to_hex(ch); + data <= to_hex(seq(index)); end architecture rtl; diff --git a/src/sequencer.vhd b/src/sequencer.vhd index f6c3ccf..b853bd8 100644 --- a/src/sequencer.vhd +++ b/src/sequencer.vhd @@ -22,7 +22,6 @@ end entity sequencer; architecture rtl of sequencer is signal index : natural := seq'low; - signal ch : character; begin @@ -36,9 +35,7 @@ begin end if; end process; - ch <= seq(index); - - data <= to_bit(ch); + data <= to_bit(seq(index)); end architecture rtl;