diff --git a/README.md b/README.md
index 4e06bbd..225acea 100644
--- a/README.md
+++ b/README.md
@@ -22,6 +22,7 @@ The next two lists will grow during further development
 * next_event[n] operator
 * until operator
 * until_ operator
+* eventually! operator (simulation, synthesis throws an error)
 
 ## PSL features not yet supported by GHDL:
 
diff --git a/formal/psl_eventually.sby b/formal/psl_eventually.sby
new file mode 100644
index 0000000..2aa85e7
--- /dev/null
+++ b/formal/psl_eventually.sby
@@ -0,0 +1,18 @@
+[tasks]
+prove
+
+[options]
+depth 25
+prove: mode bmc
+
+[engines]
+prove: smtbmc z3
+
+[script]
+prove: ghdl --std=08 pkg.vhd sequencer.vhd psl_eventually.vhd -e psl_eventually
+prep -top psl_eventually
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_eventually.vhd
diff --git a/formal/tests.mk b/formal/tests.mk
index f36911e..416bff7 100644
--- a/formal/tests.mk
+++ b/formal/tests.mk
@@ -4,4 +4,5 @@ psl_never \
 psl_next \
 psl_next_3 \
 psl_next_event \
-psl_next_event_4
+psl_next_event_4 \
+psl_until
diff --git a/src/psl_eventually.vhd b/src/psl_eventually.vhd
new file mode 100644
index 0000000..a5d3a9e
--- /dev/null
+++ b/src/psl_eventually.vhd
@@ -0,0 +1,33 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_eventually is
+  port (
+    clk : in std_logic
+  );
+end entity psl_eventually;
+
+
+architecture psl of psl_eventually is
+
+  signal a, b : std_logic;
+
+begin
+
+
+  --                              0123456789012345
+  SEQ_A : sequencer generic map ("__-__-____-_____") port map (clk, a);
+  SEQ_B : sequencer generic map ("_______-______-_") port map (clk, b);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  EVENTUALLY_a : assert always (a -> eventually! b);
+
+
+end architecture psl;