diff --git a/.github/workflows/test.yml b/.github/workflows/formal.yml
similarity index 100%
rename from .github/workflows/test.yml
rename to .github/workflows/formal.yml
diff --git a/formal/tests.mk b/formal/tests.mk
index 7fab8b7..3678c49 100644
--- a/formal/tests.mk
+++ b/formal/tests.mk
@@ -12,7 +12,6 @@ psl_next_event_e \
 psl_next_event_a \
 psl_until \
 psl_before \
-psl_eventually \
 psl_sere \
 psl_sere_overlapping_suffix_impl \
 psl_sere_non_overlapping_suffix_impl \
@@ -22,4 +21,4 @@ psl_sere_non_consecutive_goto_repetition \
 psl_cover \
 psl_sere_within \
 psl_sere_or \
-psl_sere_len_matching_and
\ No newline at end of file
+psl_sere_len_matching_and
diff --git a/sim/tests.mk b/sim/tests.mk
index 7fab8b7..1d939df 100644
--- a/sim/tests.mk
+++ b/sim/tests.mk
@@ -22,4 +22,4 @@ psl_sere_non_consecutive_goto_repetition \
 psl_cover \
 psl_sere_within \
 psl_sere_or \
-psl_sere_len_matching_and
\ No newline at end of file
+psl_sere_len_matching_and
diff --git a/src/psl_before.vhd b/src/psl_before.vhd
index ac4576b..b4a55ea 100644
--- a/src/psl_before.vhd
+++ b/src/psl_before.vhd
@@ -78,4 +78,5 @@ begin
   stop_sim(clk, 11);
   -- synthesis translate_on
 
+
 end architecture psl;
diff --git a/src/psl_eventually.vhd b/src/psl_eventually.vhd
index d33dfa4..1136ae5 100644
--- a/src/psl_eventually.vhd
+++ b/src/psl_eventually.vhd
@@ -28,7 +28,7 @@ begin
 
   -- This assertion holds
   -- This assertion leads to a GHDL synthesis crash with bug report
-  --EVENTUALLY_a : assert always (a -> eventually! b);
+  EVENTUALLY_a : assert always (a -> eventually! b);
 
   -- Stop simulation after longest running sequencer is finished
   -- Simulation only code by using pragmas
diff --git a/src/psl_logical_implication.vhd b/src/psl_logical_implication.vhd
index 866d5c0..690ced2 100644
--- a/src/psl_logical_implication.vhd
+++ b/src/psl_logical_implication.vhd
@@ -50,4 +50,5 @@ begin
   stop_sim(clk, 11);
   -- synthesis translate_on
 
+
 end architecture psl;