From b9bc7270af5b61b3a7efcaa2cefa6b1c9834030f Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Fri, 8 May 2020 02:06:02 +0200
Subject: [PATCH] Add example for next_e operator

* Add example for next_e operator
* Add formal test for next_e operator example
---
 formal/psl_next_e.sby | 18 +++++++++++
 src/psl_next_e.vhd    | 73 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 91 insertions(+)
 create mode 100644 formal/psl_next_e.sby
 create mode 100644 src/psl_next_e.vhd

diff --git a/formal/psl_next_e.sby b/formal/psl_next_e.sby
new file mode 100644
index 0000000..5da59d5
--- /dev/null
+++ b/formal/psl_next_e.sby
@@ -0,0 +1,18 @@
+[tasks]
+prove
+
+[options]
+depth 25
+prove: mode bmc
+
+[engines]
+prove: smtbmc z3
+
+[script]
+prove: ghdl --std=08 pkg.vhd sequencer.vhd psl_next_e.vhd -e psl_next_e
+prep -top psl_next_e
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_next_e.vhd
diff --git a/src/psl_next_e.vhd b/src/psl_next_e.vhd
new file mode 100644
index 0000000..8ee0808
--- /dev/null
+++ b/src/psl_next_e.vhd
@@ -0,0 +1,73 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_next_e is
+  port (
+    clk : in std_logic
+  );
+end entity psl_next_e;
+
+
+architecture psl of psl_next_e is
+
+  signal a, b : std_logic;
+  signal c, d : std_logic;
+  signal e, f : std_logic;
+  signal g, h : std_logic;
+  signal i, j : std_logic;
+  signal k, l : std_logic;
+
+begin
+
+
+  --                              01234567890
+  SEQ_A : sequencer generic map ("__-_-______") port map (clk, a);
+  SEQ_B : sequencer generic map ("_____-_-___") port map (clk, b);
+
+  --                              01234567890
+  SEQ_C : sequencer generic map ("__-_-______") port map (clk, c);
+  SEQ_D : sequencer generic map ("_____-_____") port map (clk, d);
+
+  --                              01234567890
+  SEQ_E : sequencer generic map ("__-_-______") port map (clk, e);
+  SEQ_F : sequencer generic map ("_____-----_") port map (clk, f);
+
+  --                              01234567890
+  SEQ_G : sequencer generic map ("__-_-______") port map (clk, g);
+  SEQ_H : sequencer generic map ("_____-_---_") port map (clk, h);
+
+  --                              012345678901
+  SEQ_I : sequencer generic map ("__-_-_______") port map (clk, i);
+  SEQ_J : sequencer generic map ("_____-__-___") port map (clk, j);
+
+  --                              0123456789
+  SEQ_K : sequencer generic map ("__-_-_____") port map (clk, k);
+  SEQ_L : sequencer generic map ("_______-__") port map (clk, l);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  NEXT_0_a : assert always (a -> next_e[3 to 5] (b));
+
+  -- This assertion doesn't hold at cycle 9
+  NEXT_1_a : assert always (c -> next_e[3 to 5] (d));
+
+  -- This assertion holds
+  NEXT_2_a : assert always (e -> next_e[3 to 5] (f));
+
+  -- This assertion holds
+  NEXT_3_a : assert always (g -> next_e[3 to 5] (h));
+
+   -- This assertion holds
+  NEXT_4_a : assert always (i -> next_e[3 to 5] (j));
+
+  -- This assertion holds
+  NEXT_5_a : assert always (k -> next_e[3 to 5] (l));
+
+
+end architecture psl;