From c223fc20379554247b348d203d7fc66e68f4e531 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Sat, 2 May 2020 16:55:06 +0200 Subject: [PATCH] Add 4-bit version of sequencer --- src/hex_sequencer.vhd | 44 ++++++++++++++++++++++++++++++++++ src/pkg.vhd | 56 +++++++++++++++++++++++++++++++++++++++++++ src/sequencer.vhd | 12 ++++++---- 3 files changed, 108 insertions(+), 4 deletions(-) create mode 100644 src/hex_sequencer.vhd diff --git a/src/hex_sequencer.vhd b/src/hex_sequencer.vhd new file mode 100644 index 0000000..ccdda21 --- /dev/null +++ b/src/hex_sequencer.vhd @@ -0,0 +1,44 @@ +-- Simple sequencer to generate waveforms for 4 bit std_logic_vector signals +-- Inspired by SymbioticEDA's sva-demos seq module +-- https://github.com/SymbioticEDA/sva-demos/blob/master/seq.sv + +library ieee; + use ieee.std_logic_1164.all; + +use work.pkg.all; + + +entity hex_sequencer is + generic ( + seq : string + ); + port ( + clk : in std_logic; + data : out std_logic_vector(3 downto 0) + ); +end entity hex_sequencer; + + +architecture rtl of hex_sequencer is + + signal cycle : natural := 0; + signal ch : character; + +begin + + + process (clk) is + begin + if rising_edge(clk) then + if (cycle < seq'length) then + cycle <= cycle + 1; + end if; + end if; + end process; + + ch <= seq(cycle+1); + + data <= to_hex(ch); + + +end architecture rtl; diff --git a/src/pkg.vhd b/src/pkg.vhd index 6ec3b1e..f9127af 100644 --- a/src/pkg.vhd +++ b/src/pkg.vhd @@ -15,5 +15,61 @@ package pkg is ); end component sequencer; + component hex_sequencer is + generic ( + seq : string + ); + port ( + clk : in std_logic; + data : out std_logic_vector(3 downto 0) + ); + end component hex_sequencer; + + function to_bit (a : in character) return std_logic; + function to_hex (a : in character) return std_logic_vector; + end package pkg; + + +package body pkg is + + + function to_bit (a : in character) return std_logic is + variable ret : std_logic; + begin + case a is + when '0' | '_' => ret := '0'; + when '1' | '-' => ret := '1'; + when others => ret := 'X'; + end case; + return ret; + end function to_bit; + + function to_hex (a : in character) return std_logic_vector is + variable ret : std_logic_vector(3 downto 0); + begin + case a is + when '0' | '_' => ret := x"0"; + when '1' => ret := x"1"; + when '2' => ret := x"2"; + when '3' => ret := x"3"; + when '4' => ret := x"4"; + when '5' => ret := x"5"; + when '6' => ret := x"6"; + when '7' => ret := x"7"; + when '8' => ret := x"8"; + when '9' => ret := x"9"; + when 'a' | 'A' => ret := x"A"; + when 'b' | 'B' => ret := x"B"; + when 'c' | 'C' => ret := x"C"; + when 'd' | 'D' => ret := x"D"; + when 'e' | 'E' => ret := x"E"; + when 'f' | 'F' | '-' => ret := x"F"; + when others => ret := x"X"; + end case; + return ret; + end function to_hex; + + +end package body pkg; diff --git a/src/sequencer.vhd b/src/sequencer.vhd index 6b7070c..4ef80cf 100644 --- a/src/sequencer.vhd +++ b/src/sequencer.vhd @@ -1,6 +1,12 @@ +-- Simple sequencer to generate waveforms for 1 bit std_logic signals +-- Inspired by SymbioticEDA's sva-demos seq module +-- https://github.com/SymbioticEDA/sva-demos/blob/master/seq.sv + library ieee; use ieee.std_logic_1164.all; +use work.pkg.all; + entity sequencer is generic ( @@ -32,9 +38,7 @@ begin ch <= seq(cycle+1); - data <= '0' when ch = '0' or ch = '_' else - '1' when ch = '1' or ch = '-' else - 'X'; + data <= to_bit(ch); -end architecture rtl; \ No newline at end of file +end architecture rtl;