diff --git a/README.md b/README.md
index bab90a4..033fa79 100644
--- a/README.md
+++ b/README.md
@@ -30,7 +30,7 @@ The next lists will grow during further development
 
 * always operator
 * never operator
-* logical implication operator
+* logical implication operator (->)
 * next operator
 * next[n] operator
 * next_a[i to j] operator
@@ -46,7 +46,8 @@ The next lists will grow during further development
 ### Sequential Extended Regular Expressions (SERE style)
 
 * Simple SERE
-* Overlapping suffix implication operator
+* Overlapping suffix implication operator (|->)
+* Non overlapping suffix implication operator (|=>)
 
 ## PSL features not yet supported by GHDL:
 
diff --git a/formal/psl_sere_non_overlapping_suffix_impl.sby b/formal/psl_sere_non_overlapping_suffix_impl.sby
new file mode 100644
index 0000000..a99eb89
--- /dev/null
+++ b/formal/psl_sere_non_overlapping_suffix_impl.sby
@@ -0,0 +1,18 @@
+[tasks]
+prove
+
+[options]
+depth 25
+prove: mode bmc
+
+[engines]
+prove: smtbmc z3
+
+[script]
+prove: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere_non_overlapping_suffix_impl.vhd -e psl_sere_non_overlapping_suffix_impl
+prep -top psl_sere_non_overlapping_suffix_impl
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_sere_non_overlapping_suffix_impl.vhd
diff --git a/formal/tests.mk b/formal/tests.mk
index d012148..9b63294 100644
--- a/formal/tests.mk
+++ b/formal/tests.mk
@@ -14,4 +14,5 @@ psl_until \
 psl_before \
 psl_eventually \
 psl_sere \
-psl_sere_overlapping_suffix_impl
+psl_sere_overlapping_suffix_impl \
+psl_sere_non_overlapping_suffix_impl
diff --git a/src/psl_sere_non_overlapping_suffix_impl.vhd b/src/psl_sere_non_overlapping_suffix_impl.vhd
new file mode 100644
index 0000000..544c6c7
--- /dev/null
+++ b/src/psl_sere_non_overlapping_suffix_impl.vhd
@@ -0,0 +1,39 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_sere_non_overlapping_suffix_impl is
+  port (
+    clk : in std_logic
+  );
+end entity psl_sere_non_overlapping_suffix_impl;
+
+
+architecture psl of psl_sere_non_overlapping_suffix_impl is
+
+  signal a, b : std_logic;
+
+begin
+
+
+  --                              012345678
+  SEQ_A : sequencer generic map ("--___-___") port map (clk, a);
+  SEQ_B : sequencer generic map ("_-____-__") port map (clk, b);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  SERE_0_a : assert always {a; a} |=> {not a};
+
+  -- This assertion doesn't hold at cycle 2
+  SERE_1_a : assert always {a; a} |=> {a and b};
+
+  -- This assertion holds
+  SERE_2_a : assert always {not a; a} |=> {b};
+
+
+end architecture psl;
diff --git a/src/psl_sere_overlapping_suffix_impl.vhd b/src/psl_sere_overlapping_suffix_impl.vhd
index 8544d27..651bc76 100644
--- a/src/psl_sere_overlapping_suffix_impl.vhd
+++ b/src/psl_sere_overlapping_suffix_impl.vhd
@@ -18,7 +18,7 @@ architecture psl of psl_sere_overlapping_suffix_impl is
 begin
 
 
-  --                              012345
+  --                              012345678
   SEQ_A : sequencer generic map ("--___-___") port map (clk, a);
   SEQ_B : sequencer generic map ("_-____-__") port map (clk, b);