From d904d45c9b27072ef0c0bce5b3e5bb4d743582da Mon Sep 17 00:00:00 2001 From: tmeissner Date: Tue, 2 Jun 2020 18:15:00 +0200 Subject: [PATCH] Add some examples using prev() with vectors --- README.md | 2 +- src/psl_prev.vhd | 44 +++++++++++++++++++++++++++++--------------- 2 files changed, 30 insertions(+), 16 deletions(-) diff --git a/README.md b/README.md index d90bf20..87f63ec 100644 --- a/README.md +++ b/README.md @@ -57,7 +57,7 @@ The next lists will grow during further development ### Functions -* `prev()` function (Synthesis & boolean parameter only, see [prev() example](https://github.com/tmeissner/psl_with_ghdl/blob/master/src/psl_prev.vhd)) +* `prev()` function (Synthesis only, see [prev() example](https://github.com/tmeissner/psl_with_ghdl/blob/master/src/psl_prev.vhd)) ## Not yet supported by GHDL: diff --git a/src/psl_prev.vhd b/src/psl_prev.vhd index 3a7afc6..6106938 100644 --- a/src/psl_prev.vhd +++ b/src/psl_prev.vhd @@ -1,5 +1,6 @@ library ieee; use ieee.std_logic_1164.all; + use ieee.numeric_std.all; use work.pkg.all; @@ -13,17 +14,22 @@ end entity psl_prev; architecture psl of psl_prev is - signal valid : std_logic; - signal a : std_logic; - signal d : std_logic_vector(3 downto 0); + signal valid : std_logic; + signal a : std_logic; + signal di, do : std_logic_vector(3 downto 0); + signal cnt : std_logic_vector(3 downto 0); begin - -- 01234567890123 - SEQ_VALID : sequencer generic map ("____-_-_-_-_-_") port map (clk, valid); - SEQ_A : sequencer generic map ("-__--__--__--_") port map (clk, a); - SEQ_D : hex_sequencer generic map ("00011223344556") port map (clk, d); + -- 01234567890123 + SEQ_VALID : sequencer generic map ("____-_-_-_-_-_") port map (clk, valid); + SEQ_A : sequencer generic map ("-__--__--__--_") port map (clk, a); + SEQ_DI : hex_sequencer generic map ("00011223344556") port map (clk, di); + SEQ_DO : hex_sequencer generic map ("00001020304050") port map (clk, do); + + SEQ_CNT : hex_sequencer generic map ("0123456789ABCDEF") port map (clk, cnt); + -- All is sensitive to rising edge of clk @@ -33,22 +39,21 @@ begin PREV_0_a : assert always (valid -> a = prev(a)); -- This assertion should hold - -- prev() with vector parameter isn't supported yet - -- Workaround: VHDL glue logic and simple compare - -- PREV_1_a : assert always (valid -> d = prev(d)); + PREV_1_a : assert always (valid -> di = prev(di)); - -- Workaround with VHDL glue logic generating the - -- previous value of d and simple comparing the two values + -- Workaround needed before prev() was implemented + -- With VHDL glue logic generating the + -- previous value of di and simple comparing the two values d_reg : block is - signal d_prev : std_logic_vector(d'range); + signal di_prev : std_logic_vector(di'range); begin process (clk) is begin if rising_edge(clk) then - d_prev <= d; + di_prev <= di; end if; end process; - PREV_2_a : assert always (valid -> d = d_prev); + PREV_2_a : assert always (valid -> di = di_prev); end block d_reg; -- Using prev() with additional parameter i, should return @@ -62,6 +67,15 @@ begin -- This assertion holds PREV_4_a : assert always (valid -> a = prev(a, 4)); + -- Some kind of pipeline data check, checks if do is + -- equal to di one cycle before when valid holds + -- This assertion holds + PREV_5_a : assert always (valid -> do = prev(di, 1)); + + -- Example for a simple counter check + -- This assertion holds + PREV_6_a : assert always ((cnt /= x"F") -> next (unsigned(cnt) = unsigned(prev(cnt)) + 1)); + -- Stop simulation after longest running sequencer is finished -- Simulation only code by using pragmas -- synthesis translate_off