From eaf03a8be82d6ca5d6a4866ead24feac347205db Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Fri, 22 May 2020 12:16:06 +0200
Subject: [PATCH] Add example for SERE or (|) operator

---
 README.md               |  1 +
 formal/psl_sere_or.sby  | 18 ++++++++++++++++
 formal/tests.mk         |  3 ++-
 src/psl_sere_or.vhd     | 46 +++++++++++++++++++++++++++++++++++++++++
 src/psl_sere_within.vhd |  2 +-
 5 files changed, 68 insertions(+), 2 deletions(-)
 create mode 100644 formal/psl_sere_or.sby
 create mode 100644 src/psl_sere_or.vhd

diff --git a/README.md b/README.md
index f558486..34f67dd 100644
--- a/README.md
+++ b/README.md
@@ -52,6 +52,7 @@ The next lists will grow during further development
 * Non consecutive repetition operator ([=n], [=i to j])
 * Non consecutive goto repetition operator ([->], [->n], [->i to j])
 * Length-matching and operator (&&)
+* or operator (|)
 * within operator
 
 ## Not yet supported by GHDL:
diff --git a/formal/psl_sere_or.sby b/formal/psl_sere_or.sby
new file mode 100644
index 0000000..3a92d86
--- /dev/null
+++ b/formal/psl_sere_or.sby
@@ -0,0 +1,18 @@
+[tasks]
+bmc
+
+[options]
+depth 25
+bmc: mode bmc
+
+[engines]
+bmc: smtbmc z3
+
+[script]
+bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere_or.vhd -e psl_sere_or
+prep -top psl_sere_or
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_sere_or.vhd
diff --git a/formal/tests.mk b/formal/tests.mk
index d3b24fc..3dddc1c 100644
--- a/formal/tests.mk
+++ b/formal/tests.mk
@@ -20,4 +20,5 @@ psl_sere_consecutive_repetition \
 psl_sere_non_consecutive_repeat_repetition \
 psl_sere_non_consecutive_goto_repetition \
 psl_cover \
-psl_sere_within
\ No newline at end of file
+psl_sere_within \
+psl_sere_or
\ No newline at end of file
diff --git a/src/psl_sere_or.vhd b/src/psl_sere_or.vhd
new file mode 100644
index 0000000..2e9cd3d
--- /dev/null
+++ b/src/psl_sere_or.vhd
@@ -0,0 +1,46 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_sere_or is
+  port (
+    clk : in std_logic
+  );
+end entity psl_sere_or;
+
+
+architecture psl of psl_sere_or is
+
+  signal req2, req4, busy, valid, done : std_logic;
+
+begin
+
+
+  --                                  0123456789012345678
+  SEQ_REQ2  : sequencer generic map ("_-_________________") port map (clk, req2);
+  SEQ_REQ4  : sequencer generic map ("________-__________") port map (clk, req4);
+  SEQ_BUSY  : sequencer generic map ("__----___--------__") port map (clk, busy);
+  SEQ_VALID : sequencer generic map ("___-_-____-_-_-_-__") port map (clk, valid);
+  SEQ_DONE  : sequencer generic map ("______-__________-_") port map (clk, done);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  SERE_0_a : assert always {req2 ; {valid[->2]} && {busy and not done}[+]} |=> {not busy and done};
+
+  -- This assertion holds
+  SERE_1_a : assert always {req4 ; {valid[->4]} && {busy and not done}[+]} |=> {not busy and done};
+
+  -- SERE or operato
+  -- Combination of both assertions above
+  -- This assertion holds
+  SERE_2_a : assert always {{req2 ; {valid[->2]} && {busy and not done}[+]} |
+                            {req4 ; {valid[->4]} && {busy and not done}[+]}} |=>
+                            {not busy and done};
+
+
+end architecture psl;
diff --git a/src/psl_sere_within.vhd b/src/psl_sere_within.vhd
index f968aa9..935ffa0 100644
--- a/src/psl_sere_within.vhd
+++ b/src/psl_sere_within.vhd
@@ -30,7 +30,7 @@ begin
 
   -- Occurrance of a SERE during another SERE
   -- valid has to hold 3 times during busy holds and done does't hold
-  -- This assertion doesn't hold at cycle 3
+  -- This assertion holds
   SERE_0_a : assert always {req} |=> {{valid[=3]} within {(busy and not done)[+]}; not busy and done};