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63 lines
1.4 KiB
63 lines
1.4 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_rose is
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port (
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clk : in std_logic
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);
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end entity psl_rose;
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architecture psl of psl_rose is
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signal a, b : std_logic;
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begin
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-- 01234567890
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SEQ_A : sequencer generic map ("_--__-_---_") port map (clk, a);
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SEQ_B : sequencer generic map ("_-___-_-___") port map (clk, b);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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ROSE_0_a : assert always (rose(a) -> b);
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-- This assertion holds
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ROSE_1_a : assert always {not a; a} |-> rose(a);
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-- This assertion holds
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ROSE_2_a : assert always (rose(a) -> (not prev(a) and a));
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-- Workaround needed before rose() is implemented
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-- With VHDL glue logic generating the
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-- previous value of a and simple comparing the two values
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d_reg : block is
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signal a_prev : std_logic := '0';
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begin
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process (clk) is
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begin
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if rising_edge(clk) then
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a_prev <= a;
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end if;
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end process;
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ROSE_3_a : assert always (a and not a_prev -> b);
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end block d_reg;
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-- Another workaround by using simple SERE concatenation on LHS
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ROSE_4_a : assert always {not a; a} |-> b;
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 11);
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-- synthesis translate_on
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end architecture psl;
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