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48 lines
920 B
48 lines
920 B
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_sere is
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port (
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clk : in std_logic
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);
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end entity psl_sere;
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architecture psl of psl_sere is
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signal a, b : std_logic;
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begin
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-- 012345
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SEQ_A : sequencer generic map ("--____") port map (clk, a);
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SEQ_B : sequencer generic map ("_-____") port map (clk, b);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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SERE_0_a : assert {a};
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-- This assertion holds
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SERE_1_a : assert {a; a};
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-- This assertion holds
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SERE_2_a : assert {a; a and b};
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-- This assertion doesn't hold at cycle 2
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SERE_3_a : assert always {a; a};
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 6);
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-- synthesis translate_on
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end architecture psl;
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