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82 lines
2.3 KiB
82 lines
2.3 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_before is
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port (
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clk : in std_logic
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);
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end entity psl_before;
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architecture psl of psl_before is
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signal a, b : std_logic;
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signal c, d : std_logic;
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signal e, f : std_logic;
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begin
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-- 01234567890
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SEQ_A : sequencer generic map ("_-____-____") port map (clk, a);
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SEQ_B : sequencer generic map ("___-_____-_") port map (clk, b);
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-- 01234567890
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SEQ_C : sequencer generic map ("_-___-_____") port map (clk, c);
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SEQ_D : sequencer generic map ("_____-___-_") port map (clk, d);
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-- 01234567890
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SEQ_E : sequencer generic map ("_-____-____") port map (clk, e);
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SEQ_F : sequencer generic map ("_-_______-_") port map (clk, f);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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BEFORE_0_a : assert always (a -> next (b before a));
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-- This assertion doesn't hold at cycle 5
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BEFORE_1_a : assert always (c -> next (d before c));
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-- This assertion doesn't hold at cycle 6
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BEFORE_2_a : assert always (e -> next (f before e));
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-- This is flawed variant of the former assertion
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-- because even in cycle 1 the b before a property has
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-- to hold, which is clearly not what we want
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-- This assertion doesn't hold at cycle 1
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-- Furthermore this assertion leads to a GHDL synthesis crash with bug report
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-- BEFORE_3_a : assert always (a -> (b before a));
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-- This assertion should hold but does not at cycle 3
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-- Potential GHDL bug?
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BEFORE_4_a : assert always (a -> next (b before_ a));
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-- This assertion should hold but does not at cycle 9
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-- Potential GHDL bug?
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BEFORE_5_a : assert always (c -> next (d before_ c));
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-- This assertion doesn't at cycle 6
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BEFORE_6_a : assert always (e -> next (f before_ e));
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-- This assertion holds
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BEFORE_7_a : assert always (a -> (b or next (b before a)));
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-- This assertion doesn't hold at cycle 5
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BEFORE_8_a : assert always (c -> (d or next (d before c)));
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-- This assertion holds
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BEFORE_9_a : assert always (e -> (f or next (f before e)));
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 11);
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-- synthesis translate_on
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end architecture psl;
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