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115 lines
3.5 KiB
115 lines
3.5 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_sere_consecutive_repetition is
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port (
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clk : in std_logic
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);
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end entity psl_sere_consecutive_repetition;
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architecture psl of psl_sere_consecutive_repetition is
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signal a, b, c : std_logic;
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signal d, e, f : std_logic;
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signal g, h, i : std_logic;
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begin
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-- 012345678
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SEQ_A : sequencer generic map ("_-_______") port map (clk, a);
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SEQ_B : sequencer generic map ("__----___") port map (clk, b);
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SEQ_C : sequencer generic map ("______-__") port map (clk, c);
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-- 012345
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SEQ_D : sequencer generic map ("_-____") port map (clk, d);
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SEQ_E : sequencer generic map ("______") port map (clk, e);
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SEQ_F : sequencer generic map ("__-___") port map (clk, f);
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-- 0123456789
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SEQ_G : sequencer generic map ("_-________") port map (clk, g);
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SEQ_H : sequencer generic map ("__-_-_-___") port map (clk, h);
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SEQ_I : sequencer generic map ("________-_") port map (clk, i);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- Simple SERE with repetitions done manual without operators
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-- This assertion holds
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SERE_0_a : assert always {a} |=> {b; b; b; b; c};
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-- Repetition of 4 cycles
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-- In all these cycles b has to be active
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-- This assertion holds
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SERE_1_a : assert always {a} |=> {b[*4]; c};
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-- Repetition in range of 3 to 5 cycles
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-- In all these cycles b has to be active
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-- This assertion holds
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SERE_2_a : assert always {a} |=> {b[*3 to 5]; c};
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-- Repetition of any number of cycles, including none
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-- In all these cycles b has to be active
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-- This assertion holds
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SERE_3_a : assert always {a} |=> {b[*]; c};
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-- Repetition of any number of cycles, excluding none
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-- In all these cycles b has to be active
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-- This assertion holds
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SERE_4_a : assert always {a} |=> {b[+]; c};
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-- Repetition of any number of cycles, including none
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-- In all these cycles e has to be active
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-- This assertion holds
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SERE_5_a : assert always {d} |=> {e[*]; f};
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-- Repetition of any number of cycles, excluding none
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-- In all these cycles e has to be active
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-- This assertion doesn't hold at cycle 2
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SERE_6_a : assert always {d} |=> {e[+]; f};
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-- Repetition of 3 cycles
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-- In all these cycles h has to be active
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-- This assertion doesn't hold at cycle 3
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SERE_7_a : assert always {g} |=> {h[*3]; i};
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-- Repetition in range of 2 to 4 cycles
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-- In all these cycles h has to be active
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-- This assertion doesn't hold at cycle 3
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SERE_8_a : assert always {g} |=> {h[*2 to 4]; i};
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-- Repetition of any number of cycles, including none
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-- In all these cycles h has to be active
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-- This assertion doesn't hold at cycle 3
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SERE_9_a : assert always {g} |=> {h[*]; i};
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-- Repetition of any number of cycles, exluding none
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-- In all these cycles h has to be active
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-- This assertion doesn't hold at cycle 3
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SERE_10_a : assert always {g} |=> {h[+]; i};
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-- Repetition of any 6 cycles
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-- This assertion holds
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SERE_11_a : assert always {g} |=> {[*6]; i};
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-- Upper bound can also be infinity
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-- This assertion holds
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SERE_12_a : assert always {g} |=> {[*6]; i; not i[*1 to inf]};
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-- All repetition operators can also be used with SERE
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-- This assertion holds
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SERE_13_a : assert always {g} |=> {{h; not h}[*3]; i};
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 10);
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-- synthesis translate_on
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end architecture psl;
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