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44 lines
1.0 KiB
44 lines
1.0 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_next_event_e is
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port (
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clk : in std_logic
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);
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end entity psl_next_event_e;
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architecture psl of psl_next_event_e is
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signal a, b, c : std_logic;
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begin
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-- 012345678901234
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SEQ_A : sequencer generic map ("_-______-______") port map (clk, a);
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SEQ_B : sequencer generic map ("___-__-___-__-_") port map (clk, b);
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SEQ_C : sequencer generic map ("______-___-____") port map (clk, c);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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NEXT_EVENT_0_a : assert always (a -> next_event_e(b)[1 to 2](c));
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-- This assertion doesn't hold at cycle 13
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-- This assert is similar to using next_event(b)[2](c)
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NEXT_EVENT_1_a : assert always (a -> next_event_e(b)[2 to 2](c));
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 15);
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-- synthesis translate_on
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end architecture psl;
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