diff --git a/raspiFpga/src/FiRoCtrlE.vhd b/raspiFpga/src/FiRoCtrlE.vhd index cebd7bc..a6ab317 100644 --- a/raspiFpga/src/FiRoCtrlE.vhd +++ b/raspiFpga/src/FiRoCtrlE.vhd @@ -14,6 +14,8 @@ entity FiRoCtrlE is Reset_i : in std_logic; --+ ctrl/status Start_i : in std_logic; + Wait_i : in std_logic_vector(7 downto 0); + Run_i : in std_logic_vector(7 downto 0); --+ rnd data DataValid_o : out std_logic; Data_o : out std_logic_vector(7 downto 0); @@ -28,9 +30,8 @@ end entity FiRoCtrlE; architecture rtl of FiRoCtrlE is - signal s_clk_counter : unsigned(4 downto 0); - signal s_run : std_logic; - signal s_firo_valid : std_logic; + signal s_firo_run : std_logic; + signal s_firo_valid : std_logic; type t_neumann_state is (BIT1, BIT2, BIT3, BIT4); signal s_neumann_state : t_neumann_state; @@ -46,6 +47,7 @@ architecture rtl of FiRoCtrlE is signal s_data : std_logic_vector(3 downto 0); + begin @@ -54,27 +56,31 @@ begin ControllerP : process (Clk_i) is - variable v_clk_cnt : unsigned(4 downto 0); + variable v_wait_cnt : unsigned(7 downto 0); + variable v_run_cnt : unsigned(7 downto 0); begin if (rising_edge(Clk_i)) then if (s_register_state = SLEEP) then - v_clk_cnt := (others => '1'); - s_run <= '0'; + v_wait_cnt := unsigned(Wait_i); + v_run_cnt := unsigned(Run_i); + s_firo_run <= '0'; s_firo_valid <= '0'; else s_firo_valid <= '0'; - if (v_clk_cnt = 23 and s_run = '0') then - s_run <= '1'; - v_clk_cnt := (others => '1'); - end if; - if (v_clk_cnt = 12 and s_run = '1') then - s_run <= '0'; - v_clk_cnt := (others => '1'); + if (v_wait_cnt = 0) then + s_firo_run <= '1'; + else + v_wait_cnt := v_wait_cnt - 1; end if; - if (v_clk_cnt = 13 and s_run = '1') then - s_firo_valid := '1'; + if (v_run_cnt = 0) then + s_firo_run <= '0'; + elsif (v_run_cnt = 1) then + s_firo_valid <= '1'; + else + if (v_wait_cnt = 0) then + v_run_cnt := v_run_cnt - 1; + end if; end if; - v_clk_cnt := v_clk_cnt - 1; end if; end if; end process ControllerP; @@ -86,9 +92,6 @@ begin if (rising_edge(Clk_i)) then if (Reset_i = '0') then s_neumann_state <= BIT1; - --s_neumann_buffer <= "000"; - --s_register_enable <= '0'; - --s_register_din <= "00"; else case s_neumann_state is diff --git a/raspiFpga/src/RaspiFpgaCtrlE.vhd b/raspiFpga/src/RaspiFpgaCtrlE.vhd index 4eda220..9549409 100644 --- a/raspiFpga/src/RaspiFpgaCtrlE.vhd +++ b/raspiFpga/src/RaspiFpgaCtrlE.vhd @@ -7,20 +7,22 @@ library ieee; entity RaspiFpgaCtrlE is port ( --+ System if - Rst_n_i : in std_logic; - Clk_i : in std_logic; + Rst_n_i : in std_logic; + Clk_i : in std_logic; --+ local register if - LocalWen_o : out std_logic; - LocalRen_o : out std_logic; - LocalAdress_o : out std_logic_vector(7 downto 0); - LocalData_i : in std_logic_vector(7 downto 0); - LocalData_o : out std_logic_vector(7 downto 0); - LocalAck_i : in std_logic; - LocalError_i : in std_logic; + LocalWen_o : out std_logic; + LocalRen_o : out std_logic; + LocalAdress_o : out std_logic_vector(7 downto 0); + LocalData_i : in std_logic_vector(7 downto 0); + LocalData_o : out std_logic_vector(7 downto 0); + LocalAck_i : in std_logic; + LocalError_i : in std_logic; --+ EFB if - EfbSpiIrq_i : in std_logic; + EfbSpiIrq_i : in std_logic; --+ RNG if RngStart_o : out std_logic; + RngWait_o : out std_logic_vector(7 downto 0); + RngRun_o : out std_logic_vector(7 downto 0); RngDataValid_i : in std_logic; RngData_i : in std_logic_vector(7 downto 0) ); @@ -43,6 +45,11 @@ architecture rtl of RaspiFpgaCtrlE is constant C_SPIIRQ : std_logic_vector(7 downto 0) := x"5C"; --* interrupt request constant C_SPIIRQEN : std_logic_vector(7 downto 0) := x"5D"; --* interrupt request enable + --+ Register file addresses + constant C_REG_RNGSTATUS : natural := 0; + constant C_REG_RNGWAIT : natural := 1; + constant C_REG_RNGRUN : natural := 2; + constant C_REG_RNGDATA : natural := 3; type t_cmdctrl_fsm is (IDLE, INIT_SET, INIT_ACK, TXDR_SET, TXDR_ACK, INT_WAIT, RXDR_SET, RXDR_ACK, INT_CLEAR_SET, INT_CLEAR_ACK); @@ -89,6 +96,8 @@ begin x"FF"; + --+ FSM to write/request data from the wishbone master + --+ State logic/register CmdCtrlP : process (Clk_i) is begin if (rising_edge(Clk_i)) then @@ -150,6 +159,8 @@ begin end process CmdCtrlP; + --+ FSM to write/request data from the wishbone master + --+ Registered outputs CmdRegisterP : process (Clk_i) is begin if (rising_edge(Clk_i)) then @@ -196,27 +207,41 @@ begin end process CmdRegisterP; + --+ Register bank write enable s_register_we <= LocalAck_i when s_cmdctrl_fsm = RXDR_ACK and s_spi_frame = WRITE_DATA else '0'; + --+ Register bank 127x8 RegisterFileP : process (Clk_i) is begin if (rising_edge(Clk_i)) then if (Rst_n_i = '0') then - s_register <= (others => (others => '0')); + s_register <= (others => (others => '0')); + s_register(C_REG_RNGWAIT) <= x"0F"; + s_register(C_REG_RNGRUN) <= x"0F"; else - s_register(0)(0) <= '0'; --* reset RNG start after each clock cycle + s_register(C_REG_RNGSTATUS)(0) <= '0'; -- reset RNG start after each clock cycle if (s_register_we = '1') then s_register(s_register_address) <= LocalData_i; end if; - --+ register RNG data + -- register RNG data if (RngDataValid_i = '1') then - s_register(0)(1) <= '1'; - s_register(1) <= RngData_i; + s_register(C_REG_RNGSTATUS)(1) <= '1'; + s_register(C_REG_RNGDATA) <= RngData_i; + end if; + -- clear RNG done flag when RNG was started + if (s_register(C_REG_RNGSTATUS)(0) = '1') then + s_register(C_REG_RNGSTATUS)(1) <= '0'; end if; end if; end if; end process RegisterFileP; + --+ RNG control outputs + RngStart_o <= s_register(C_REG_RNGSTATUS)(0); + RngWait_o <= s_register(C_REG_RNGWAIT); + RngRun_o <= s_register(C_REG_RNGRUN); + + end architecture rtl; diff --git a/raspiFpga/src/RaspiFpgaE.vhd b/raspiFpga/src/RaspiFpgaE.vhd index 0ef80ae..7113d52 100644 --- a/raspiFpga/src/RaspiFpgaE.vhd +++ b/raspiFpga/src/RaspiFpgaE.vhd @@ -2,8 +2,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ---library machxo2; --- use machxo2.components.all; +library machxo2; + use machxo2.components.all; @@ -73,6 +73,8 @@ architecture rtl of RaspiFpgaE is EfbSpiIrq_i : in std_logic; --+ RNG if RngStart_o : out std_logic; + RngWait_o : out std_logic_vector(7 downto 0); + RngRun_o : out std_logic_vector(7 downto 0); RngDataValid_i : in std_logic; RngData_i : in std_logic_vector(7 downto 0) ); @@ -89,6 +91,8 @@ architecture rtl of RaspiFpgaE is Reset_i : in std_logic; --+ ctrl/status Start_i : in std_logic; + Wait_i : in std_logic_vector(7 downto 0); + Run_i : in std_logic_vector(7 downto 0); --+ rnd data DataValid_o : out std_logic; Data_o : out std_logic_vector(7 downto 0); @@ -180,6 +184,8 @@ architecture rtl of RaspiFpgaE is --+ RNG signals signal s_rng_start : std_logic; + signal s_rng_wait : std_logic_vector(7 downto 0); + signal s_rng_run : std_logic_vector(7 downto 0); signal s_rng_data_valid : std_logic; signal s_rng_data : std_logic_vector(7 downto 0); signal s_firo_run : std_logic; @@ -284,7 +290,13 @@ begin LocalAck_i => s_local_ack, LocalError_i => '0', --+ EFB if - EfbSpiIrq_i => s_efb_irq + EfbSpiIrq_i => s_efb_irq, + --+ RNG if + RngStart_o => s_rng_start, + RngWait_o => s_rng_wait, + RngRun_o => s_rng_run, + RngDataValid_i => s_rng_data_valid, + RngData_i => s_rng_data ); @@ -298,6 +310,8 @@ begin Reset_i => s_sys_rst, --+ ctrl/status Start_i => s_rng_start, + Wait_i => s_rng_wait, + Run_i => s_rng_run, --+ rnd data DataValid_o => s_rng_data_valid, Data_o => s_rng_data,