From 91306866a966b476b79e2742743aad0f749f3b17 Mon Sep 17 00:00:00 2001
From: tmeissner <programming@goodcleanfun.de>
Date: Sat, 6 Dec 2014 12:46:39 +0100
Subject: [PATCH] fixed swapped clk & rst connections on WishBoneMasterE module

---
 raspiFpga/src/RaspiFpgaE.vhd | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/raspiFpga/src/RaspiFpgaE.vhd b/raspiFpga/src/RaspiFpgaE.vhd
index ec6f39a..28c6de9 100644
--- a/raspiFpga/src/RaspiFpgaE.vhd
+++ b/raspiFpga/src/RaspiFpgaE.vhd
@@ -209,8 +209,8 @@ begin
     )
     port map (
       --+ wishbone system if
-      WbRst_i       => s_wb_clk,
-      WbClk_i       => s_wb_rst,
+      WbRst_i       => s_wb_rst,
+      WbClk_i       => s_wb_clk,
       --+ wishbone outputs
       WbCyc_o       => s_wb_cyc,
       WbStb_o       => s_wb_stb,