diff --git a/eagle/pcb/usbtrng.brd b/eagle/pcb/usbtrng.brd
index b5feffd..aef9cb3 100644
--- a/eagle/pcb/usbtrng.brd
+++ b/eagle/pcb/usbtrng.brd
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-VCC
-GND
-3V3
-XC JTAG
-GPIO
-usb-avr-cpld v0.1
-www.github.com/tmeissner
+
+GND
+VCC
+3V3
+GPIO
+CPLD JTAG
+USB-AVR-CPLD experimental board v0.1
+(c) 2012 by T. Meissner - www.github.com/tmeissner
+6
+1
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+
+<b>AVR Devices</b><p>
+Configurable logic, microcontrollers, nonvolatile memories<p>
+Based on the following sources:<p>
+<ul>
+<li>www.atmel.com
+<li>CD-ROM : Configurable Logic Microcontroller Nonvolatile Memory
+<li>CadSoft download site, www.cadsoft.de or www.cadsoftusa.com , file at90smcu_v400.zip
+<li>avr.lbr
+</ul>
+<author>Revised by librarian@cadsoft.de</author>
+
+
+<b>8S2</b> 8-lead, 0.208 Body<p>
+Plastic Small Outline Package (EIAJ)<br>
+Source: http://www.atmel.com/dyn/resources/prod_documents/2535S.pdf
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@@ -1701,82 +1760,76 @@ http://www.linear-tech.com<p>
-<b>EAGLE Design Rules Prototypen für PCB-POOL(R)</b>
-<p>
-Wir haben in diesem DRU File alle notwendigen Design Einstellungen vorgenommen, damit Sie Ihre Leiterplatte
-gemaess unseren Mindestanforderungen im Standard bestellen koennen. Die Optionen Shapes und Misc sind dabei nicht relevant.
-Der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden.
-Bitte beachten Sie, daß die Mindesteinstellungen nicht geaendert werden, da ansonsten keine Gewaehrleistung für eine
-fehlerfreie Produktion übernommen werden kann.<br>
-Abzudeckende Vias koennen in Masks (unter Limit) eingestellt werden.
-</p>Ihr Beta LAYOUT Team
-<p><p>
-<b>EAGLE Design Rules Prototypes to use with PCB-POOL(R)</b>
+<br><br>
+<b>EAGLE Design Rules für Q-PCB.de Prototypen</b>
<p>
-The design rules in this DRU file have been set to cover our minimum standard requirements, the options Shapes and Misc are not
-relevant. Values for Roundness (Shapes) can be chosen freely. Please do not change these minimum
-requirements to avoid problems during production.<br>
-Covered vias can be set in Masks (Limit).
-
-</p>Your Beta LAYOUT Team
-
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+In dieser DRU-Datei wurden die empfohlenen Einstellungen für Q-PCB.de vorgenommen.<br>
+Die Werte bei SHAPES und MISC sind für die Produktion nicht relevant.<br>
+Der definierte Lagenaufbau entspricht dem Pool-Standard. Siehe hierzu auch das Dokument QD04-02. <br>
+Das Abdecken der Durchkontaktierungen (Via-Clogging) findet ab Bohrgröße 16mil standardmässig statt. Diesen Wert können Sie auf Wunsch unter MASK/LIMIT ändern.<br>
+Bitte ändern Sie ansonsten keine Einstellungen, da ansonsten eine reibungslose Produktion nicht gewährleistet ist.<p>
+Bei Rückfragen steht Ihnen unser Team gerne zur Verfügung.<br>
+Vielen Dank.<p>
+<b>Q-PCB.de - ein Service der Q-print electronic GmbH</b>
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diff --git a/eagle/pcb/usbtrng.sch b/eagle/pcb/usbtrng.sch
index c927f60..d728172 100644
--- a/eagle/pcb/usbtrng.sch
+++ b/eagle/pcb/usbtrng.sch
@@ -15917,6 +15917,158 @@ Source: http://cds.linear.com/docs/Datasheet/1763ff.pdf
+
+<b>AVR Devices</b><p>
+Configurable logic, microcontrollers, nonvolatile memories<p>
+Based on the following sources:<p>
+<ul>
+<li>www.atmel.com
+<li>CD-ROM : Configurable Logic Microcontroller Nonvolatile Memory
+<li>CadSoft download site, www.cadsoft.de or www.cadsoftusa.com , file at90smcu_v400.zip
+<li>avr.lbr
+</ul>
+<author>Revised by librarian@cadsoft.de</author>
+
+
+<b>8M1-A-MLF (VDFN)</b> 6 x 5 mm<p>
+Source: http://www.atmel.com/dyn/resources/prod_documents/doc3500.pdf
+
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+>NAME
+>VALUE
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+<b>8S2</b> 8-lead, 0.208 Body<p>
+Plastic Small Outline Package (EIAJ)<br>
+Source: http://www.atmel.com/dyn/resources/prod_documents/2535S.pdf
+
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+>VALUE
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+<b>16-megabit 2.5V or 2.7V DataFlash</b><p>
+Source: http://www.atmel.com/dyn/resources/prod_documents/doc3500.pdf
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