From 90bd0911d3581ded0e62d79cc457da908c0929a8 Mon Sep 17 00:00:00 2001 From: tmeissner Date: Thu, 28 Oct 2021 07:58:03 +0200 Subject: [PATCH] README:clarify project focus & intention --- README.md | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 150f24e..f5c4282 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,11 @@ +The original repository is now located on my own git-server at [https://git.goodcleanfun.de/tmeissner/verification_ip](https://git.goodcleanfun.de/tmeissner/verification_ip) +It is mirrored to github with every push, so both should be in sync. + # verification_ip Verification IPs for simulation & formal verification of various selected protocols. All tests are done with [GHDL](https://github.com/ghdl/ghdl) and [SymbiYosys](https://github.com/YosysHQ/SymbiYosys), a front-end for formal verification flows based on [Yosys](https://github.com/YosysHQ/yosys). +*The components in this repository are not intended as productional code. They are created out of personal interest and to find out what one can achieve with current state of open source tools, expecially in the VHDL domain.* + ### wishbone -Simple VIP for the wishbone bus protocol. At the moment support of classic single read / write cycles only. +Simple VIP for the wishbone bus protocol. First goal is functional coverage to detect valid transfer cycles and their variants. Currently support of classic single read / write cycles only.