commit 94394c123e1aacb0d94e5d4833281c6262df94b1
Author: tmeissner <programming@goodcleanfun.de>
Date:   Thu Oct 28 00:05:27 2021 +0200

    Initial commit

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+# verification_ip
+
+Verification IPs for simulation & formal verification of various selected protocols. All tests are done with [GHDL](https://github.com/ghdl/ghdl) and  [SymbiYosys](https://github.com/YosysHQ/SymbiYosys), a front-end for formal verification flows based on [Yosys](https://github.com/YosysHQ/yosys).
+
+### wishbone
+Simple VIP for the wishbone bus protocol. At the moment support of classic single read / write cycles only.